[RISCV] Remove intrinsic declarations in tests, NFC #167474

jacquesguan · 2025-11-11T09:11:14Z

As @mshockwave mentioned in #156415, we don't need to declare intrinsics in tests now, this pr removes them.

llvmbot · 2025-11-11T09:12:13Z

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-risc-v

Author: Jianjian Guan (jacquesguan)

Changes

As @mshockwave mentioned in #156415, we don't need to declare intrinsics in tests now, this pr removes them.

Patch is 13.07 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/167474.diff

1039 Files Affected:

(modified) llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll (-17)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll (-45)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll (-16)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll (-5)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll (-1)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll (-6)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll (-4)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll (-8)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll (-20)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll (-8)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll (-20)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll (-520)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll (-390)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vle.ll (-444)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlm.ll (-14)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll (-392)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll (-1484)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vlse.ll (-518)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll (-392)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll (-1484)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vse.ll (-407)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsm.ll (-24)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei-rv64.ll (-364)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsoxei.ll (-1378)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsse.ll (-481)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei-rv64.ll (-364)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vsuxei.ll ()
(modified) llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll ()
(modified) llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll ()
(modified) llvm/test/CodeGen/RISCV/abds-neg.ll ()
(modified) llvm/test/CodeGen/RISCV/abds.ll (-15)
(modified) llvm/test/CodeGen/RISCV/abdu-neg.ll (-15)
(modified) llvm/test/CodeGen/RISCV/abdu.ll (-15)
(modified) llvm/test/CodeGen/RISCV/addcarry.ll (-3)
(modified) llvm/test/CodeGen/RISCV/alloca.ll (-3)
(modified) llvm/test/CodeGen/RISCV/allow-check.ll (-3)
(modified) llvm/test/CodeGen/RISCV/arith-with-overflow.ll (-5)
(modified) llvm/test/CodeGen/RISCV/atomic-signext.ll (-5)
(modified) llvm/test/CodeGen/RISCV/bfloat-arith.ll (-13)
(modified) llvm/test/CodeGen/RISCV/bfloat-convert.ll (-8)
(modified) llvm/test/CodeGen/RISCV/bitreverse-shift.ll (-5)
(modified) llvm/test/CodeGen/RISCV/bswap-bitreverse.ll (-8)
(modified) llvm/test/CodeGen/RISCV/bswap-shift.ll (-4)
(modified) llvm/test/CodeGen/RISCV/clear-cache.ll (-2)
(modified) llvm/test/CodeGen/RISCV/copy-frameindex.mir (-2)
(modified) llvm/test/CodeGen/RISCV/copysign-casts.ll (-4)
(modified) llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll (-13)
(modified) llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll (-36)
(modified) llvm/test/CodeGen/RISCV/double-arith-strict.ll (-8)
(modified) llvm/test/CodeGen/RISCV/double-arith.ll (-12)
(modified) llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll (-4)
(modified) llvm/test/CodeGen/RISCV/double-convert-strict.ll (-14)
(modified) llvm/test/CodeGen/RISCV/double-convert.ll (-8)
(modified) llvm/test/CodeGen/RISCV/double-fcmp-strict.ll (-2)
(modified) llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll (-54)
(modified) llvm/test/CodeGen/RISCV/double-intrinsics.ll (-60)
(modified) llvm/test/CodeGen/RISCV/double-maximum-minimum.ll (-4)
(modified) llvm/test/CodeGen/RISCV/double-round-conv-sat.ll (-10)
(modified) llvm/test/CodeGen/RISCV/double-round-conv.ll (-5)
(modified) llvm/test/CodeGen/RISCV/double-zfa.ll (-13)
(modified) llvm/test/CodeGen/RISCV/double_reduct.ll (-22)
(modified) llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll (-13)
(modified) llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll (-1)
(modified) llvm/test/CodeGen/RISCV/fixed-csr.ll (-2)
(modified) llvm/test/CodeGen/RISCV/float-arith-strict.ll (-8)
(modified) llvm/test/CodeGen/RISCV/float-arith.ll (-12)
(modified) llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll (-4)
(modified) llvm/test/CodeGen/RISCV/float-convert-strict.ll (-12)
(modified) llvm/test/CodeGen/RISCV/float-convert.ll (-8)
(modified) llvm/test/CodeGen/RISCV/float-fcmp-strict.ll (-2)
(modified) llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll (-54)
(modified) llvm/test/CodeGen/RISCV/float-intrinsics.ll (-60)
(modified) llvm/test/CodeGen/RISCV/float-maximum-minimum.ll (-4)
(modified) llvm/test/CodeGen/RISCV/float-round-conv-sat.ll (-10)
(modified) llvm/test/CodeGen/RISCV/float-round-conv.ll (-5)
(modified) llvm/test/CodeGen/RISCV/float-select-verify.ll (-1)
(modified) llvm/test/CodeGen/RISCV/float-zfa.ll (-14)
(modified) llvm/test/CodeGen/RISCV/flt-rounds.ll (-2)
(modified) llvm/test/CodeGen/RISCV/fmax-fmin.ll (-4)
(modified) llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll (-4)
(modified) llvm/test/CodeGen/RISCV/fpclamptosat.ll (-12)
(modified) llvm/test/CodeGen/RISCV/fpenv.ll (-2)
(modified) llvm/test/CodeGen/RISCV/frame.ll (-2)
(modified) llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll (-2)
(modified) llvm/test/CodeGen/RISCV/frm-dependency.ll (-2)
(modified) llvm/test/CodeGen/RISCV/get-register-invalid.ll (-2)
(modified) llvm/test/CodeGen/RISCV/get-register-noreserve.ll (-4)
(modified) llvm/test/CodeGen/RISCV/get-register-reserve.ll (-2)
(modified) llvm/test/CodeGen/RISCV/half-arith-strict.ll (-6)
(modified) llvm/test/CodeGen/RISCV/half-arith.ll (-13)
(modified) llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll (-4)
(modified) llvm/test/CodeGen/RISCV/half-convert-strict.ll (-17)
(modified) llvm/test/CodeGen/RISCV/half-convert.ll (-8)
(modified) llvm/test/CodeGen/RISCV/half-fcmp-strict.ll (-2)
(modified) llvm/test/CodeGen/RISCV/half-intrinsics.ll (-53)
(modified) llvm/test/CodeGen/RISCV/half-maximum-minimum.ll (-4)
(modified) llvm/test/CodeGen/RISCV/half-round-conv-sat.ll (-10)
(modified) llvm/test/CodeGen/RISCV/half-round-conv.ll (-5)
(modified) llvm/test/CodeGen/RISCV/half-zfa.ll (-25)
(modified) llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll (-2)
(modified) llvm/test/CodeGen/RISCV/i64-icmp.ll (-1)
(modified) llvm/test/CodeGen/RISCV/iabs.ll (-6)
(modified) llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll (-6)
(modified) llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll (-2)
(modified) llvm/test/CodeGen/RISCV/intrinsics/trap.ll (-3)
(modified) llvm/test/CodeGen/RISCV/libcall-tail-calls.ll (-14)
(modified) llvm/test/CodeGen/RISCV/live-sp.mir (-1)
(modified) llvm/test/CodeGen/RISCV/llvm.exp10.ll (-13)
(modified) llvm/test/CodeGen/RISCV/llvm.frexp.ll (-15)
(modified) llvm/test/CodeGen/RISCV/machine-combiner.ll (-23)
(modified) llvm/test/CodeGen/RISCV/machine-cse.ll (-6)
(modified) llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll (-2)
(modified) llvm/test/CodeGen/RISCV/memcpy-inline.ll (-4)
(modified) llvm/test/CodeGen/RISCV/memcpy.ll (-3)
(modified) llvm/test/CodeGen/RISCV/memmove.ll (-2)
(modified) llvm/test/CodeGen/RISCV/memset-inline.ll (-5)
(modified) llvm/test/CodeGen/RISCV/min-max.ll (-32)
(modified) llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll (-3)
(modified) llvm/test/CodeGen/RISCV/neg-abs.ll (-3)
(modified) llvm/test/CodeGen/RISCV/overflow-intrinsic-optimizations.ll (-1)
(modified) llvm/test/CodeGen/RISCV/pei-crash.ll (-2)
(modified) llvm/test/CodeGen/RISCV/pr135206.ll (-1)
(modified) llvm/test/CodeGen/RISCV/pr56457.ll (-2)
(modified) llvm/test/CodeGen/RISCV/pr69586.ll (-5)
(modified) llvm/test/CodeGen/RISCV/pr92193.ll (-1)
(modified) llvm/test/CodeGen/RISCV/prefetch.ll (-3)
(modified) llvm/test/CodeGen/RISCV/push-pop-popret.ll (-6)
(modified) llvm/test/CodeGen/RISCV/readcyclecounter.ll (-2)
(modified) llvm/test/CodeGen/RISCV/readsteadycounter.ll (-2)
(modified) llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll (-2)
(modified) llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll (-8)
(modified) llvm/test/CodeGen/RISCV/replace-with-veclib-sleef-scalable.ll (-42)
(modified) llvm/test/CodeGen/RISCV/riscv-zihintpause.ll (-2)
(modified) llvm/test/CodeGen/RISCV/rotl-rotr.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv32p.ll (-16)
(modified) llvm/test/CodeGen/RISCV/rv32xtheadbb.ll (-12)
(modified) llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll (-2)
(modified) llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll (-8)
(modified) llvm/test/CodeGen/RISCV/rv32zbb.ll (-24)
(modified) llvm/test/CodeGen/RISCV/rv32zbc-intrinsic.ll (-2)
(modified) llvm/test/CodeGen/RISCV/rv32zbc-zbkc-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv32zbkb-intrinsic.ll (-8)
(modified) llvm/test/CodeGen/RISCV/rv32zbkx-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv32zknd-intrinsic-autoupgrade.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv32zkne-intrinsic-autoupgrade.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll (-21)
(modified) llvm/test/CodeGen/RISCV/rv32zksed-intrinsic-autoupgrade.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64-double-convert.ll (-2)
(modified) llvm/test/CodeGen/RISCV/rv64-float-convert.ll (-2)
(modified) llvm/test/CodeGen/RISCV/rv64-half-convert.ll (-2)
(modified) llvm/test/CodeGen/RISCV/rv64-patchpoint.ll (-3)
(modified) llvm/test/CodeGen/RISCV/rv64-stackmap-args.ll (-1)
(modified) llvm/test/CodeGen/RISCV/rv64-stackmap-frame-setup.ll (-1)
(modified) llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll (-1)
(modified) llvm/test/CodeGen/RISCV/rv64-stackmap.ll (-3)
(modified) llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll (-2)
(modified) llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll (-14)
(modified) llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll (-2)
(modified) llvm/test/CodeGen/RISCV/rv64-trampoline.ll (-2)
(modified) llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll (-3)
(modified) llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll (-3)
(modified) llvm/test/CodeGen/RISCV/rv64p.ll (-16)
(modified) llvm/test/CodeGen/RISCV/rv64xtheadbb.ll (-12)
(modified) llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll (-8)
(modified) llvm/test/CodeGen/RISCV/rv64zbb.ll (-24)
(modified) llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll (-8)
(modified) llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll (-8)
(modified) llvm/test/CodeGen/RISCV/rv64zbkx-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll (-8)
(modified) llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll (-6)
(modified) llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll (-17)
(modified) llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll (-17)
(modified) llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll (-5)
(modified) llvm/test/CodeGen/RISCV/rvv/abd.ll (-12)
(modified) llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll (-30)
(modified) llvm/test/CodeGen/RISCV/rvv/abs-vp.ll (-48)
(modified) llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll (-6)
(modified) llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll (-7)
(modified) llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll (-5)
(modified) llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll (-9)
(modified) llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll (-22)
(modified) llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll (-48)
(modified) llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll (-15)
(modified) llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll (-34)
(modified) llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll (-44)
(modified) llvm/test/CodeGen/RISCV/rvv/combine-sats.ll (-4)
(modified) llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll (-2)
(modified) llvm/test/CodeGen/RISCV/rvv/commutable.ll (-49)
(modified) llvm/test/CodeGen/RISCV/rvv/compressstore.ll (-33)
(modified) llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll (-1)
(modified) llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll (-22)
(modified) llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll (-71)
(modified) llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll (-23)
(modified) llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll (-49)
(modified) llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll (-22)
(modified) llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll (-71)
(modified) llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir (-2)
(modified) llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll (-6)
(modified) llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll (-12)
(modified) llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll (-2)
(modified) llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll (-24)
(modified) llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll (-2)
(modified) llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll (-15)
(modified) llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll (-15)
(modified) llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll (-15)
(modified) llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll (-21)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll (-33)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll (-36)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll (-9)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll (-36)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll (-6)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll (-28)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll (-6)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll (-28)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll (-12)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-int.ll (-16)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll (-36)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll (-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll (-36)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll (-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll (-36)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll (-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll (-12)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll (-16)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll (-23)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll (-15)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll (-15)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll (-28)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll (-26)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll (-26)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll (-26)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll (-26)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll (-24)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll (-16)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll (-14)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll (-10)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll (-6)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll (-28)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll (-6)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll (-28)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll (-15)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll (-15)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll (-15)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll (-15)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll (-15)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll (-40)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll (-15)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll (-7)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll (-22)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll (-16)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll (-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll (-10)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll (-22)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll (-16)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll (-10)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll (-23)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll (-17)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll (-30)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll (-69)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll (-68)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll (-28)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll (-20)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll (-7)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll (-16)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll (-143)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll (-147)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll (-577)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll (-114)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll (-28)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll (-28)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll (-28)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll (-28)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll (-9)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll (-12)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll (-9)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll (-14)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll (-6)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll (-22)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll (-6)

diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
index 4246aa545dd0e..ae6418ee97ba5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
@@ -121,8 +121,6 @@ define double @fdiv_d(double %a, double %b) nounwind {
   ret double %1
 }
 
-declare double @llvm.sqrt.f64(double)
-
 define double @fsqrt_d(double %a) nounwind {
 ; CHECKIFD-LABEL: fsqrt_d:
 ; CHECKIFD:       # %bb.0:
@@ -150,8 +148,6 @@ define double @fsqrt_d(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.copysign.f64(double, double)
-
 define double @fsgnj_d(double %a, double %b) nounwind {
 ; CHECKIFD-LABEL: fsgnj_d:
 ; CHECKIFD:       # %bb.0:
@@ -261,8 +257,6 @@ define double @fsgnjn_d(double %a, double %b) nounwind {
   ret double %2
 }
 
-declare double @llvm.fabs.f64(double)
-
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
 define double @fabs_d(double %a, double %b) nounwind {
@@ -305,8 +299,6 @@ define double @fabs_d(double %a, double %b) nounwind {
   ret double %3
 }
 
-declare double @llvm.minnum.f64(double, double)
-
 define double @fmin_d(double %a, double %b) nounwind {
 ; CHECKIFD-LABEL: fmin_d:
 ; CHECKIFD:       # %bb.0:
@@ -334,8 +326,6 @@ define double @fmin_d(double %a, double %b) nounwind {
   ret double %1
 }
 
-declare double @llvm.maxnum.f64(double, double)
-
 define double @fmax_d(double %a, double %b) nounwind {
 ; CHECKIFD-LABEL: fmax_d:
 ; CHECKIFD:       # %bb.0:
@@ -363,8 +353,6 @@ define double @fmax_d(double %a, double %b) nounwind {
   ret double %1
 }
 
-declare double @llvm.minimumnum.f64(double, double)
-
 define double @fminimumnum_d(double %a, double %b) nounwind {
 ; CHECKIFD-LABEL: fminimumnum_d:
 ; CHECKIFD:       # %bb.0:
@@ -392,8 +380,6 @@ define double @fminimumnum_d(double %a, double %b) nounwind {
   ret double %1
 }
 
-declare double @llvm.maximumnum.f64(double, double)
-
 define double @fmaximumnum_d(double %a, double %b) nounwind {
 ; CHECKIFD-LABEL: fmaximumnum_d:
 ; CHECKIFD:       # %bb.0:
@@ -421,8 +407,6 @@ define double @fmaximumnum_d(double %a, double %b) nounwind {
   ret double %1
 }
 
-declare double @llvm.fma.f64(double, double, double)
-
 define double @fmadd_d(double %a, double %b, double %c) nounwind {
 ; CHECKIFD-LABEL: fmadd_d:
 ; CHECKIFD:       # %bb.0:
@@ -771,7 +755,6 @@ define double @fnmadd_d_3(double %a, double %b, double %c) nounwind {
   ret double %neg
 }
 
-
 define double @fnmadd_nsz(double %a, double %b, double %c) nounwind {
 ; CHECKIFD-LABEL: fnmadd_nsz:
 ; CHECKIFD:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
index 4b0acda839ad6..906e4bc41d960 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
@@ -10,8 +10,6 @@
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -global-isel  \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
-declare double @llvm.sqrt.f64(double)
-
 define double @sqrt_f64(double %a) nounwind {
 ; CHECKIFD-LABEL: sqrt_f64:
 ; CHECKIFD:       # %bb.0:
@@ -81,8 +79,6 @@ define double @powi_f64(double %a, i32 %b) nounwind {
   ret double %1
 }
 
-declare double @llvm.sin.f64(double)
-
 define double @sin_f64(double %a) nounwind {
 ; RV32IFD-LABEL: sin_f64:
 ; RV32IFD:       # %bb.0:
@@ -123,8 +119,6 @@ define double @sin_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.cos.f64(double)
-
 define double @cos_f64(double %a) nounwind {
 ; RV32IFD-LABEL: cos_f64:
 ; RV32IFD:       # %bb.0:
@@ -257,8 +251,6 @@ define double @sincos_f64(double %a) nounwind {
   ret double %3
 }
 
-declare double @llvm.pow.f64(double, double)
-
 define double @pow_f64(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: pow_f64:
 ; RV32IFD:       # %bb.0:
@@ -299,8 +291,6 @@ define double @pow_f64(double %a, double %b) nounwind {
   ret double %1
 }
 
-declare double @llvm.exp.f64(double)
-
 define double @exp_f64(double %a) nounwind {
 ; RV32IFD-LABEL: exp_f64:
 ; RV32IFD:       # %bb.0:
@@ -341,8 +331,6 @@ define double @exp_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.exp2.f64(double)
-
 define double @exp2_f64(double %a) nounwind {
 ; RV32IFD-LABEL: exp2_f64:
 ; RV32IFD:       # %bb.0:
@@ -423,8 +411,6 @@ define double @exp10_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.log.f64(double)
-
 define double @log_f64(double %a) nounwind {
 ; RV32IFD-LABEL: log_f64:
 ; RV32IFD:       # %bb.0:
@@ -465,8 +451,6 @@ define double @log_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.log10.f64(double)
-
 define double @log10_f64(double %a) nounwind {
 ; RV32IFD-LABEL: log10_f64:
 ; RV32IFD:       # %bb.0:
@@ -507,8 +491,6 @@ define double @log10_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.log2.f64(double)
-
 define double @log2_f64(double %a) nounwind {
 ; RV32IFD-LABEL: log2_f64:
 ; RV32IFD:       # %bb.0:
@@ -549,8 +531,6 @@ define double @log2_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.fma.f64(double, double, double)
-
 define double @fma_f64(double %a, double %b, double %c) nounwind {
 ; CHECKIFD-LABEL: fma_f64:
 ; CHECKIFD:       # %bb.0:
@@ -578,8 +558,6 @@ define double @fma_f64(double %a, double %b, double %c) nounwind {
   ret double %1
 }
 
-declare double @llvm.fmuladd.f64(double, double, double)
-
 define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
 ; CHECKIFD-LABEL: fmuladd_f64:
 ; CHECKIFD:       # %bb.0:
@@ -621,8 +599,6 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
   ret double %1
 }
 
-declare double @llvm.fabs.f64(double)
-
 define double @fabs_f64(double %a) nounwind {
 ; CHECKIFD-LABEL: fabs_f64:
 ; CHECKIFD:       # %bb.0:
@@ -644,8 +620,6 @@ define double @fabs_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.minnum.f64(double, double)
-
 define double @minnum_f64(double %a, double %b) nounwind {
 ; CHECKIFD-LABEL: minnum_f64:
 ; CHECKIFD:       # %bb.0:
@@ -673,8 +647,6 @@ define double @minnum_f64(double %a, double %b) nounwind {
   ret double %1
 }
 
-declare double @llvm.maxnum.f64(double, double)
-
 define double @maxnum_f64(double %a, double %b) nounwind {
 ; CHECKIFD-LABEL: maxnum_f64:
 ; CHECKIFD:       # %bb.0:
@@ -702,8 +674,6 @@ define double @maxnum_f64(double %a, double %b) nounwind {
   ret double %1
 }
 
-declare double @llvm.copysign.f64(double, double)
-
 define double @copysign_f64(double %a, double %b) nounwind {
 ; CHECKIFD-LABEL: copysign_f64:
 ; CHECKIFD:       # %bb.0:
@@ -731,8 +701,6 @@ define double @copysign_f64(double %a, double %b) nounwind {
   ret double %1
 }
 
-declare double @llvm.floor.f64(double)
-
 define double @floor_f64(double %a) nounwind {
 ; RV32IFD-LABEL: floor_f64:
 ; RV32IFD:       # %bb.0:
@@ -773,8 +741,6 @@ define double @floor_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.ceil.f64(double)
-
 define double @ceil_f64(double %a) nounwind {
 ; RV32IFD-LABEL: ceil_f64:
 ; RV32IFD:       # %bb.0:
@@ -815,8 +781,6 @@ define double @ceil_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.trunc.f64(double)
-
 define double @trunc_f64(double %a) nounwind {
 ; RV32IFD-LABEL: trunc_f64:
 ; RV32IFD:       # %bb.0:
@@ -857,8 +821,6 @@ define double @trunc_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.rint.f64(double)
-
 define double @rint_f64(double %a) nounwind {
 ; RV32IFD-LABEL: rint_f64:
 ; RV32IFD:       # %bb.0:
@@ -899,8 +861,6 @@ define double @rint_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.nearbyint.f64(double)
-
 define double @nearbyint_f64(double %a) nounwind {
 ; RV32IFD-LABEL: nearbyint_f64:
 ; RV32IFD:       # %bb.0:
@@ -941,8 +901,6 @@ define double @nearbyint_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.round.f64(double)
-
 define double @round_f64(double %a) nounwind {
 ; RV32IFD-LABEL: round_f64:
 ; RV32IFD:       # %bb.0:
@@ -983,8 +941,6 @@ define double @round_f64(double %a) nounwind {
   ret double %1
 }
 
-declare double @llvm.roundeven.f64(double)
-
 define double @roundeven_f64(double %a) nounwind {
 ; RV32IFD-LABEL: roundeven_f64:
 ; RV32IFD:       # %bb.0:
@@ -1025,7 +981,6 @@ define double @roundeven_f64(double %a) nounwind {
   ret double %1
 }
 
-declare i1 @llvm.is.fpclass.f64(double, i32)
 define i1 @isnan_d_fpclass(double %x) {
 ; CHECKIFD-LABEL: isnan_d_fpclass:
 ; CHECKIFD:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
index 3222849641baf..06eeaa8d4e503 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
@@ -121,8 +121,6 @@ define float @fdiv_s(float %a, float %b) nounwind {
   ret float %1
 }
 
-declare float @llvm.sqrt.f32(float)
-
 define float @fsqrt_s(float %a) nounwind {
 ; CHECKIF-LABEL: fsqrt_s:
 ; CHECKIF:       # %bb.0:
@@ -150,8 +148,6 @@ define float @fsqrt_s(float %a) nounwind {
   ret float %1
 }
 
-declare float @llvm.copysign.f32(float, float)
-
 define float @fsgnj_s(float %a, float %b) nounwind {
 ; CHECKIF-LABEL: fsgnj_s:
 ; CHECKIF:       # %bb.0:
@@ -270,8 +266,6 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
   ret float %3
 }
 
-declare float @llvm.fabs.f32(float)
-
 define float @fabs_s(float %a, float %b) nounwind {
 ; CHECKIF-LABEL: fabs_s:
 ; CHECKIF:       # %bb.0:
@@ -311,8 +305,6 @@ define float @fabs_s(float %a, float %b) nounwind {
   ret float %3
 }
 
-declare float @llvm.minimumnum.f32(float, float)
-
 define float @fminimumnum_s(float %a, float %b) nounwind {
 ; CHECKIF-LABEL: fminimumnum_s:
 ; CHECKIF:       # %bb.0:
@@ -340,8 +332,6 @@ define float @fminimumnum_s(float %a, float %b) nounwind {
   ret float %1
 }
 
-declare float @llvm.maximumnum.f32(float, float)
-
 define float @fmaximumnum_s(float %a, float %b) nounwind {
 ; CHECKIF-LABEL: fmaximumnum_s:
 ; CHECKIF:       # %bb.0:
@@ -369,8 +359,6 @@ define float @fmaximumnum_s(float %a, float %b) nounwind {
   ret float %1
 }
 
-declare float @llvm.minnum.f32(float, float)
-
 define float @fmin_s(float %a, float %b) nounwind {
 ; CHECKIF-LABEL: fmin_s:
 ; CHECKIF:       # %bb.0:
@@ -398,8 +386,6 @@ define float @fmin_s(float %a, float %b) nounwind {
   ret float %1
 }
 
-declare float @llvm.maxnum.f32(float, float)
-
 define float @fmax_s(float %a, float %b) nounwind {
 ; CHECKIF-LABEL: fmax_s:
 ; CHECKIF:       # %bb.0:
@@ -427,8 +413,6 @@ define float @fmax_s(float %a, float %b) nounwind {
   ret float %1
 }
 
-declare float @llvm.fma.f32(float, float, float)
-
 define float @fmadd_s(float %a, float %b, float %c) nounwind {
 ; CHECKIF-LABEL: fmadd_s:
 ; CHECKIF:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll b/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
index 31a78d4f72ceb..8ced3155c58ec 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
@@ -8,11 +8,6 @@
 ; RUN: llc -mtriple=riscv64 -global-isel -mattr=+zbb -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV64ZBB
 
-declare i8 @llvm.abs.i8(i8, i1 immarg)
-declare i16 @llvm.abs.i16(i16, i1 immarg)
-declare i32 @llvm.abs.i32(i32, i1 immarg)
-declare i64 @llvm.abs.i64(i64, i1 immarg)
-
 define i8 @abs8(i8 %x) {
 ; RV32I-LABEL: abs8:
 ; RV32I:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
index 48d72108335e4..cd1e95e88ab8a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vacopy.ll
@@ -4,7 +4,6 @@
 ; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
-declare void @llvm.va_copy(ptr, ptr)
 define void @test_va_copy(ptr %dest_list, ptr %src_list) {
   ; RV32I-LABEL: name: test_va_copy
   ; RV32I: bb.1 (%ir-block.0):
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
index 74961d12c1c85..ad1544db84391 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
@@ -25,9 +25,6 @@
 ; The nounwind attribute is omitted for some of the tests, to check that CFI
 ; directives are correctly generated.
 
-declare void @llvm.va_start(ptr)
-declare void @llvm.va_end(ptr)
-
 declare void @notdead(ptr)
 
 ; Although frontends are recommended to not generate va_arg due to the lack of
@@ -453,7 +450,6 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind {
   ret i32 %1
 }
 
-
 define i32 @va1_va_arg(ptr %fmt, ...) nounwind {
   ; RV32-LABEL: name: va1_va_arg
   ; RV32: bb.1 (%ir-block.0):
@@ -1249,8 +1245,6 @@ define void @va3_caller() nounwind {
  ret void
 }
 
-declare void @llvm.va_copy(ptr, ptr)
-
 define i32 @va4_va_copy(i32 %argno, ...) nounwind {
   ; ILP32-LABEL: name: va4_va_copy
   ; ILP32: bb.1 (%ir-block.0):
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
index 46d1661983c6a..f70e27906474a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
@@ -1749,7 +1749,6 @@ define signext i32 @rotl_32_mask_shared(i32 signext %a, i32 signext %b, i32 sign
   %3 = add i32 %1, %2
   ret i32 %3
 }
-declare i32 @llvm.fshl.i32(i32, i32, i32)
 
 define signext i64 @rotl_64_mask_shared(i64 signext %a, i64 signext %b, i64 signext %amt) nounwind {
 ; RV32I-LABEL: rotl_64_mask_shared:
@@ -1984,7 +1983,6 @@ define signext i64 @rotl_64_mask_shared(i64 signext %a, i64 signext %b, i64 sign
   %3 = add i64 %1, %2
   ret i64 %3
 }
-declare i64 @llvm.fshl.i64(i64, i64, i64)
 
 define signext i32 @rotr_32_mask_shared(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {
 ; RV32I-LABEL: rotr_32_mask_shared:
@@ -2050,7 +2048,6 @@ define signext i32 @rotr_32_mask_shared(i32 signext %a, i32 signext %b, i32 sign
   %3 = add i32 %1, %2
   ret i32 %3
 }
-declare i32 @llvm.fshr.i32(i32, i32, i32)
 
 define signext i64 @rotr_64_mask_shared(i64 signext %a, i64 signext %b, i64 signext %amt) nounwind {
 ; RV32I-LABEL: rotr_64_mask_shared:
@@ -2291,7 +2288,6 @@ define signext i64 @rotr_64_mask_shared(i64 signext %a, i64 signext %b, i64 sign
   %3 = add i64 %1, %2
   ret i64 %3
 }
-declare i64 @llvm.fshr.i64(i64, i64, i64)
 
 define signext i32 @rotl_32_mask_multiple(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {
 ; RV32I-LABEL: rotl_32_mask_multiple:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
index da95481a5e588..83cf228402295 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
@@ -111,8 +111,6 @@ define i64 @xnor_i64(i64 %a, i64 %b) nounwind {
   ret i64 %xor
 }
 
-declare i32 @llvm.fshl.i32(i32, i32, i32)
-
 define i32 @rol_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: rol_i32:
 ; RV32I:       # %bb.0:
@@ -133,8 +131,6 @@ define i32 @rol_i32(i32 %a, i32 %b) nounwind {
 ; This test is presented here in case future expansions of the Bitmanip
 ; extensions introduce instructions suitable for this pattern.
 
-declare i64 @llvm.fshl.i64(i64, i64, i64)
-
 define i64 @rol_i64(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: rol_i64:
 ; CHECK:       # %bb.0:
@@ -187,8 +183,6 @@ define i64 @rol_i64(i64 %a, i64 %b) nounwind {
   ret i64 %or
 }
 
-declare i32 @llvm.fshr.i32(i32, i32, i32)
-
 define i32 @ror_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: ror_i32:
 ; RV32I:       # %bb.0:
@@ -209,8 +203,6 @@ define i32 @ror_i32(i32 %a, i32 %b) nounwind {
 ; This test is presented here in case future expansions of the Bitmanip
 ; extensions introduce instructions suitable for this pattern.
 
-declare i64 @llvm.fshr.i64(i64, i64, i64)
-
 define i64 @ror_i64(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: ror_i64:
 ; CHECK:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
index 0b376dd779887..a59a46bdd0e7f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
@@ -4,8 +4,6 @@
 ; RUN: llc -mtriple=riscv32 -global-isel -mattr=+zbb -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32ZBB
 
-declare i32 @llvm.ctlz.i32(i32, i1)
-
 define i32 @ctlz_i32(i32 %a) nounwind {
 ; RV32I-LABEL: ctlz_i32:
 ; RV32I:       # %bb.0:
@@ -57,8 +55,6 @@ define i32 @ctlz_i32(i32 %a) nounwind {
   ret i32 %1
 }
 
-declare i64 @llvm.ctlz.i64(i64, i1)
-
 define i64 @ctlz_i64(i64 %a) nounwind {
 ; RV32I-LABEL: ctlz_i64:
 ; RV32I:       # %bb.0:
@@ -153,8 +149,6 @@ define i64 @ctlz_i64(i64 %a) nounwind {
   ret i64 %1
 }
 
-declare i32 @llvm.cttz.i32(i32, i1)
-
 define i32 @cttz_i32(i32 %a) nounwind {
 ; RV32I-LABEL: cttz_i32:
 ; RV32I:       # %bb.0:
@@ -197,8 +191,6 @@ define i32 @cttz_i32(i32 %a) nounwind {
   ret i32 %1
 }
 
-declare i64 @llvm.cttz.i64(i64, i1)
-
 define i64 @cttz_i64(i64 %a) nounwind {
 ; RV32I-LABEL: cttz_i64:
 ; RV32I:       # %bb.0:
@@ -276,8 +268,6 @@ define i64 @cttz_i64(i64 %a) nounwind {
   ret i64 %1
 }
 
-declare i32 @llvm.ctpop.i32(i32)
-
 define i32 @ctpop_i32(i32 %a) nounwind {
 ; RV32I-LABEL: ctpop_i32:
 ; RV32I:       # %bb.0:
@@ -312,8 +302,6 @@ define i32 @ctpop_i32(i32 %a) nounwind {
   ret i32 %1
 }
 
-declare i64 @llvm.ctpop.i64(i64)
-
 define i64 @ctpop_i64(i64 %a) nounwind {
 ; RV32I-LABEL: ctpop_i64:
 ; RV32I:       # %bb.0:
@@ -737,8 +725,6 @@ define i64 @maxu_i64(i64 %a, i64 %b) nounwind {
   ret i64 %cond
 }
 
-declare i32 @llvm.abs.i32(i32, i1 immarg)
-
 define i32 @abs_i32(i32 %x) {
 ; RV32I-LABEL: abs_i32:
 ; RV32I:       # %bb.0:
@@ -756,8 +742,6 @@ define i32 @abs_i32(i32 %x) {
   ret i32 %abs
 }
 
-declare i64 @llvm.abs.i64(i64, i1 immarg)
-
 define i64 @abs_i64(i64 %x) {
 ; CHECK-LABEL: abs_i64:
 ; CHECK:       # %bb.0:
@@ -805,8 +789,6 @@ define i64 @zexth_i64(i64 %a) nounwind {
   ret i64 %and
 }
 
-declare i32 @llvm.bswap.i32(i32)
-
 define i32 @bswap_i32(i32 %a) nounwind {
 ; RV32I-LABEL: bswap_i32:
 ; RV32I:       # %bb.0:
@@ -831,8 +813,6 @@ define i32 @bswap_i32(i32 %a) nounwind {
   ret i32 %1
 }
 
-declare i64 @llvm.bswap.i64(i64)
-
 define i64 @bswap_i64(i64 %a) {
 ; RV32I-LABEL: bswap_i64:
 ; RV32I:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
index b7f84ba696c26..8a21889334fb8 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
@@ -102,8 +102,6 @@ define i64 @xnor_i64(i64 %a, i64 %b) nounwind {
   ret i64 %xor
 }
 
-declare i32 @llvm.fshl.i32(i32, i32, i32)
-
 define signext i32 @rol_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: rol_i32:
 ; RV64I:       # %bb.0:
@@ -161,8 +159,6 @@ define signext i32 @rol_i32_neg_constant_rhs(i32 signext %a) nounwind {
   ret i32 %1
 }
 
-declare i64 @llvm.fshl.i64(i64, i64, i64)
-
 define i64 @rol_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: rol_i64:
 ; RV64I:       # %bb.0:
@@ -180,8 +176,6 @@ define i64 @rol_i64(i64 %a, i64 %b) nounwind {
   ret i64 %or
 }
 
-declare i32 @llvm.fshr.i32(i32, i32, i32)
-
 define signext i32 @ror_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: ror_i32:
 ; RV64I:       # %bb.0:
@@ -239,8 +233,6 @@ define signext i32 @ror_i32_neg_constant_rhs(i32 signext %a) nounwind {
   ret i32 %1
 }
 
-declare i64 @llvm.fshr.i64(i64, i64, i64)
-
 define i64 @ror_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: ror_i64:
 ; RV64I:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
index 2dd3bb3119dd3..daac8440e5763 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
@@ -4,8 +4,6 @@
 ; RUN: llc -mtriple=riscv64 -global-isel -mattr=+zbb -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZBB
 
-declare i32 @llvm.ctlz.i32(i32, i1)
-
 ; FIXME: We don't need the sh...
[truncated]

eopXD

Changes look good.

topperc

LGTM

lukel97

LGTM. I presume you grepped for declare @llvm.*?

lukel97 · 2025-11-12T06:16:55Z

llvm/test/CodeGen/RISCV/live-sp.mir

  ; Function Attrs: nofree nosync nounwind readnone willreturn
-  declare ptr @llvm.returnaddress(i32 immarg) #0

  attributes #0 = { nofree nosync nounwind readnone willreturn }


Suggested change

; Function Attrs: nofree nosync nounwind readnone willreturn

declare ptr @llvm.returnaddress(i32 immarg) #0

attributes #0 = { nofree nosync nounwind readnone willreturn }

lukel97 · 2025-11-12T06:17:42Z

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

I think this and attribute #4 can be removed

lukel97 · 2025-11-12T06:18:01Z

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

Same here, the attributes can be removed?

lukel97 · 2025-11-12T06:18:14Z

llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir

@@ -13,8 +13,6 @@
    ret <vscale x 2 x float> %0
  }

-  declare <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64) #1
-
  attributes #0 = { "target-features"="+v" }
  attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) "target-features"="+v" }


Remove the leftover attributes

lukel97 · 2025-11-12T06:18:37Z

llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir

  ; Function Attrs: argmemonly nofree nosync nounwind readonly willreturn
-  declare <vscale x 8 x i64> @llvm.masked.load.nxv8i64.p0(ptr, i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i64>) #1

  attributes #0 = { nounwind "target-features"="+v" }
  attributes #1 = { argmemonly nofree nosync nounwind readonly willreturn "target-features"="+v" }


Suggested change

; Function Attrs: argmemonly nofree nosync nounwind readonly willreturn

declare <vscale x 8 x i64> @llvm.masked.load.nxv8i64.p0(ptr, i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i64>) #1

attributes #0 = { nounwind "target-features"="+v" }

attributes #1 = { argmemonly nofree nosync nounwind readonly willreturn "target-features"="+v" }

attributes #0 = { nounwind "target-features"="+v" }

lukel97 · 2025-11-12T06:18:57Z

llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir

@@ -58,7 +58,6 @@
  }

  ; Function Attrs: nounwind readnone speculatable willreturn


Suggested change

; Function Attrs: nounwind readnone speculatable willreturn

arsenm · 2025-11-13T04:13:12Z

I'm not sure bulk removing them is the best idea. They are still canonically printed, and this breaks auto-upgrade if there are ever any future intrinsic changes

jacquesguan · 2025-11-14T07:07:18Z

I'm not sure bulk removing them is the best idea. They are still canonically printed, and this breaks auto-upgrade if there are ever any future intrinsic changes

I don't understand about the part that 'breaks auto-upgrade'.

eopXD · 2025-11-14T07:33:15Z

I think what @arsenm means is that compiler with clang -emit-llvm still emits the declaration, and a batch-update to all existing test cases will still add back those declarations you are trying to remove here. So probably need to fix somewhere for the declaration gen.

arsenm · 2025-11-15T04:56:44Z

I'm not sure bulk removing them is the best idea. They are still canonically printed, and this breaks auto-upgrade if there are ever any future intrinsic changes

I don't understand about the part that 'breaks auto-upgrade'.

If you make a change to the intrinsic signature, if you have the declaration in the file the test will continue working. That does not happen if you remove the manual declaration and you added a new argument, for example

4vtomat · 2025-11-15T05:59:39Z

As there're some PRs merged in this period, do you mind to do another round of removal lol?

github-actions · 2025-11-19T12:23:38Z

🐧 Linux x64 Test Results

186368 tests passed
4859 tests skipped

jacquesguan

I'm not sure bulk removing them is the best idea. They are still canonically printed, and this breaks auto-upgrade if there are ever any future intrinsic changes

I don't understand about the part that 'breaks auto-upgrade'.

If you make a change to the intrinsic signature, if you have the declaration in the file the test will continue working. That does not happen if you remove the manual declaration and you added a new argument, for example

In my option, If we changed the intrinsic signature, we should also update the related test at the same time. The test case should cover the new version rather than the old one.

jacquesguan

As there're some PRs merged in this period, do you mind to do another round of removal lol?

Updated.

jacquesguan requested review from eopXD, mshockwave and topperc November 11, 2025 09:11

llvmbot added backend:RISC-V llvm:globalisel labels Nov 11, 2025

eopXD approved these changes Nov 12, 2025

View reviewed changes

topperc approved these changes Nov 12, 2025

View reviewed changes

lukel97 approved these changes Nov 12, 2025

View reviewed changes

jacquesguan force-pushed the riscv-remove-intrinsic-declare branch from f0f6f6b to 816753a Compare November 12, 2025 06:49

jacquesguan added 4 commits November 19, 2025 17:05

[RISCV] Remove intrinsic declarations in tests, NFC

2167266

Remove redundant attribute

39292e1

Remove redundant comment

ca3a979

rebase and update

f9f709a

jacquesguan force-pushed the riscv-remove-intrinsic-declare branch from 8e3800f to f9f709a Compare November 19, 2025 11:38

jacquesguan commented Nov 20, 2025

View reviewed changes

		@@ -58,7 +58,6 @@
		}

		; Function Attrs: nounwind readnone speculatable willreturn

[RISCV] Remove intrinsic declarations in tests, NFC #167474

Are you sure you want to change the base?

[RISCV] Remove intrinsic declarations in tests, NFC #167474

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🐧 Linux x64 Test Results

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llvmbot commented Nov 11, 2025 •

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