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I2C DV fix #21

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Merged
marnovandermaas merged 2 commits into from
Feb 18, 2025
Merged

I2C DV fix #21

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2c1272e
DV paths fixes for I2C under VCS
marnovandermaas Dec 20, 2024
e1ac853
Apply patches to lowrisc_ip
marnovandermaas Feb 14, 2025
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2 changes: 1 addition & 1 deletion hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
import_testplans: ["hw/dv/tools/dvsim/testplans/tl_device_access_types_wo_intg_testplan.hjson"]
import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_wo_intg_testplan.hjson"]
testpoints: [
{
name: tl_intg_err
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2 changes: 1 addition & 1 deletion hw/vendor/lowrisc_ip/ip/aon_timer/dv/tb.sv
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Expand Up @@ -50,7 +50,7 @@ module tb;

`DV_ALERT_IF_CONNECT()

assign alert_tx = '0;
assign alert_tx = '0;

aon_timer dut (
.clk_i (clk),
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8 changes: 4 additions & 4 deletions hw/vendor/lowrisc_ip/ip/i2c/data/i2c_testplan.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -3,10 +3,10 @@
// SPDX-License-Identifier: Apache-2.0
{
name: "i2c"
import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
"hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
"hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
"hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
//"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
"i2c_sec_cm_testplan.hjson"]
testpoints: [
//-----------------------------------------------
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10 changes: 5 additions & 5 deletions hw/vendor/lowrisc_ip/ip/i2c/dv/i2c_sim_cfg.hjson
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Expand Up @@ -18,17 +18,17 @@
fusesoc_core: lowrisc:dv:i2c_sim:0.1

// Testplan hjson file.
testplan: "{proj_root}/hw/ip/i2c/data/i2c_testplan.hjson"
testplan: "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/data/i2c_testplan.hjson"

// RAL spec - used to generate the RAL model.
ral_spec: "{proj_root}/hw/ip/i2c/data/i2c.hjson"
ral_spec: "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/data/i2c.hjson"

// Import additional common sim cfg files.
import_cfgs: [// Project wide common sim cfg file
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
// Common CIP test lists
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
//"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson"]
Expand All @@ -37,7 +37,7 @@
sim_tops: ["i2c_bind", "sec_cm_prim_onehot_check_bind"]

// Add coverage exclusion file
vcs_cov_excl_files: ["{proj_root}/hw/ip/i2c/dv/cov/i2c_cov_excl.el"]
vcs_cov_excl_files: ["{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/cov/i2c_cov_excl.el"]

// Default iterations for all tests - each test entry can override this.
reseed: 50
Expand All @@ -53,7 +53,7 @@
overrides: [
{
name: default_vcs_cov_cfg_file
value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/dv/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/ip/i2c/dv/cov/cov_excl.cfg"
value: "-cm_hier {proj_root}/hw/vendor/lowrisc_ip/dv/tools/vcs/cover.cfg+{proj_root}/hw/vendor/lowrisc_ip/dv/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/cov/cov_excl.cfg"
}
]

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13 changes: 13 additions & 0 deletions hw/vendor/patches/lowrisc_ip/dv_tools/0003-Fix-Paths.patch
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,19 @@ index 2fe58c6..799831f 100644
tests: [
{
name: "{name}_stress_all_with_rand_reset"
diff --git a/dvsim/testplans/tl_device_access_types_testplan.hjson b/dvsim/testplans/tl_device_access_types_testplan.hjson
index f405656..e4ce794 100644
--- a/dvsim/testplans/tl_device_access_types_testplan.hjson
+++ b/dvsim/testplans/tl_device_access_types_testplan.hjson
@@ -2,7 +2,7 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
- import_testplans: ["hw/dv/tools/dvsim/testplans/tl_device_access_types_wo_intg_testplan.hjson"]
+ import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_wo_intg_testplan.hjson"]
testpoints: [
{
name: tl_intg_err
diff --git a/ralgen/ralgen.py b/ralgen/ralgen.py
index 4281666..a9760ea 100755
--- a/ralgen/ralgen.py
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48 changes: 46 additions & 2 deletions hw/vendor/patches/lowrisc_ip/i2c/0003-Fix-DV.patch
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,16 @@ diff --git a/dv/i2c_sim_cfg.hjson b/dv/i2c_sim_cfg.hjson
index 4edfc9c..bbeb8b0 100644
--- a/dv/i2c_sim_cfg.hjson
+++ b/dv/i2c_sim_cfg.hjson
@@ -25,13 +25,13 @@
@@ -18,26 +18,26 @@
fusesoc_core: lowrisc:dv:i2c_sim:0.1

// Testplan hjson file.
- testplan: "{proj_root}/hw/ip/i2c/data/i2c_testplan.hjson"
+ testplan: "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/data/i2c_testplan.hjson"
Comment on lines +24 to +25
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@alees24 alees24 Dec 20, 2024

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I do not know why, but for me the testplan path needs to remain unmodified.

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@marnovandermaas marnovandermaas Feb 14, 2025

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I cannot see how this works for you. The hw/ip directory in the repo only contains core_ibex, rom and sram.


// RAL spec - used to generate the RAL model.
- ral_spec: "{proj_root}/hw/ip/i2c/data/i2c.hjson"
+ ral_spec: "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/data/i2c.hjson"

// Import additional common sim cfg files.
import_cfgs: [// Project wide common sim cfg file
Expand All @@ -30,13 +39,29 @@ index 4edfc9c..bbeb8b0 100644
- "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
- "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"]
+ "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
+ "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
+ //"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
+ "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
+ "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
+ "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson"]

// Add additional tops for simulation.
sim_tops: ["i2c_bind", "sec_cm_prim_onehot_check_bind"]

// Add coverage exclusion file
- vcs_cov_excl_files: ["{proj_root}/hw/ip/i2c/dv/cov/i2c_cov_excl.el"]
+ vcs_cov_excl_files: ["{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/cov/i2c_cov_excl.el"]

// Default iterations for all tests - each test entry can override this.
reseed: 50
@@ -53,7 +53,7 @@
overrides: [
{
name: default_vcs_cov_cfg_file
- value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/dv/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/ip/i2c/dv/cov/cov_excl.cfg"
+ value: "-cm_hier {proj_root}/hw/vendor/lowrisc_ip/dv/tools/vcs/cover.cfg+{proj_root}/hw/vendor/lowrisc_ip/dv/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/cov/cov_excl.cfg"
}
]

diff --git a/dv/tb/tb.sv b/dv/tb/tb.sv
index 5ae4816..f70036f 100644
--- a/dv/tb/tb.sv
Expand All @@ -60,3 +85,22 @@ index 5ae4816..f70036f 100644
.cio_scl_i (cio_scl ),
.cio_scl_o (/*hardcoded to 0*/ ),
.cio_scl_en_o (cio_scl_en ),
diff --git a/data/i2c_testplan.hjson b/i2c/data/i2c_testplan.hjson
index 07120ff..f194499 100644
--- a/data/i2c_testplan.hjson
+++ b/data/i2c_testplan.hjson
@@ -3,10 +3,10 @@
// SPDX-License-Identifier: Apache-2.0
{
name: "i2c"
- import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
- "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
- "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
- "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
+ import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
+ //"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
+ "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
+ "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
"i2c_sec_cm_testplan.hjson"]
testpoints: [
//-----------------------------------------------