SPI host and UART block-level DV fixes

hw/vendor/lowrisc_ip.vendor.hjson

@@ -12,6 +12,11 @@
     }
 
     mapping: [
+        {from: "util/autogen_banner.py", to: "util/autogen_banner.py", patch_dir: "autogen_banner"},
+        {from: "util/autogen_testutils.py", to: "util/autogen_testutils.py"},
+        {from: "util/autogen_testutils", to: "util/autogen_testutils", patch_dir: "autogen_testutils"},
+        {from: "util/make_new_dif.py", to: "util/make_new_dif.py", patch_dir: "make_new_dif_py"},
+        {from: "util/make_new_dif",    to: "util/make_new_dif", patch_dir: "make_new_dif"},
         {from: "util/ipgen.py",        to: "util/ipgen.py"},
         {from: "util/ipgen",           to: "util/ipgen"},
         {from: "util/tlgen.py",        to: "util/tlgen.py"},

hw/vendor/lowrisc_ip/ip/spi_host/dv/env/seq_lib/spi_host_base_vseq.sv

@@ -114,7 +114,7 @@ class spi_host_base_vseq extends cip_base_vseq #(
       end
       [cfg.seq_cfg.host_spi_middle_clkdiv+1 : 16'hFFF] : cfg.csr_spinwait_timeout_ns *= 5;
       [16'hFFF+1 : cfg.seq_cfg.host_spi_max_clkdiv] : cfg.csr_spinwait_timeout_ns *= 10;
-      default : `uvm_fatal(`gfn, $sformatf("spi_config_regs.clkdiv[0]=0x%0x is out range"))
+      default : `uvm_fatal(`gfn, $sformatf("spi_config_regs.clkdiv[0]=0x%0x is out range", spi_config_regs.clkdiv[0]))
     endcase
   endfunction
 

hw/vendor/lowrisc_ip/ip/spi_host/dv/env/spi_host_env_pkg.sv

@@ -154,7 +154,7 @@ package spi_host_env_pkg;
   } spi_host_intr_test_t;
 
   // alerts
-  parameter uint NUM_ALERTS = 1;
+  parameter uint NUM_ALERTS = 0;
   parameter string LIST_OF_ALERTS[] = {};
 
   // functions

hw/vendor/lowrisc_ip/ip/spi_host/dv/spi_host_sim_cfg.hjson

@@ -30,7 +30,7 @@
                 "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
                 "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
                 "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/mem_tests.hjson",
-                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
+                //"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
                 "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
                 "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                 //"{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson", // TODO(#18886): enable for V3

hw/vendor/lowrisc_ip/ip/uart/dv/env/uart_env_pkg.sv

@@ -25,7 +25,7 @@ package uart_env_pkg;
   parameter uint MAX_RX_WATERMARK_LVL = 7;
   parameter uint MAX_TX_WATERMARK_LVL = 7;
   // alerts
-  parameter uint NUM_ALERTS = 1;
+  parameter uint NUM_ALERTS = 0;
   parameter string LIST_OF_ALERTS[] = {};
 
   typedef enum int {

hw/vendor/lowrisc_ip/ip/uart/dv/uart_sim_cfg.hjson

@@ -28,7 +28,7 @@
                 "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
                 // Common CIP test lists
                 "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
-                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
+                //"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
                 "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
                 "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson",
                 "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",

hw/vendor/lowrisc_ip/util/make_new_dif/BUILD

@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors (OpenTitan project).
+# Copyright lowRISC contributors (Sunburst project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 

hw/vendor/patches/lowrisc_ip/autogen_banner/0001_Project_Name.patch

@@ -0,0 +1,13 @@
+diff --git a/autogen_banner.py b/autogen_banner.py
+index 00a104e..5aed6a6 100644
+--- a/autogen_banner.py
++++ b/autogen_banner.py
+@@ -5,7 +5,7 @@
+ from textwrap import fill
+
+ LICENSE_BANNER = (
++    "Copyright lowRISC contributors (Sunburst project).\n"
+-    "Copyright lowRISC contributors (OpenTitan project).\n"
+     "Licensed under the Apache License, Version 2.0, see LICENSE for details.\n"
+     "SPDX-License-Identifier: Apache-2.0")
+

hw/vendor/patches/lowrisc_ip/autogen_testutils/0001_Repo_Structure.patch

@@ -0,0 +1,36 @@
+diff --git a/gen.py b/gen.py
+index 4183e52..72a25ce 100644
+--- a/gen.py
++++ b/gen.py
+@@ -13,10 +13,10 @@
+ from make_new_dif.ip import Ip
+ from mako.template import Template
+
++# This file is $REPO_TOP/hw/vendor/lowrisc_ip/util/autogen_testutils/gen.py, so it takes six parent()
+-# This file is $REPO_TOP/util/autogen_testutils.py, so it takes two parent()
+ # calls to get back to the top.
++IP_TOP = Path(__file__).resolve().parent.parent.parent
++REPO_TOP = IP_TOP.parent.parent.parent
+-REPO_TOP = Path(__file__).resolve().parent.parent.parent
+-
+
+ def gen_testutils(ips_with_difs: List[Ip]) -> None:
+     """Generate testutils libraries that are rendered from Mako templates.
+@@ -31,7 +31,7 @@
+     ips_with_difs.sort(key=lambda ip: ip.name_snake)
+
+     # Define input/output directories.
++    testutils_templates_dir = IP_TOP / "util/autogen_testutils/templates"
+-    testutils_templates_dir = REPO_TOP / "util/autogen_testutils/templates"
+     autogen_testutils_dir = REPO_TOP / "sw/device/lib/testing/autogen"
+
+     # Create output directories if needed.
+@@ -57,7 +57,7 @@
+     # Format autogenerated file with clang-format.
+     try:
+         subprocess.check_call(
++            ["clang-format", "-i", "--"] + testutilses
+-            ["./bazelisk.sh", "run", "//quality:clang_format_fix", "--"] + testutilses
+         )
+     except subprocess.CalledProcessError:
+         logging.error(

hw/vendor/patches/lowrisc_ip/make_new_dif/0001_Remove_Alerts_Add_Build.patch

@@ -0,0 +1,65 @@
+diff --git a/BUILD b/BUILD
+new file mode 100644
+index 6b0351d..0000000
+--- /dev/null
++++ b/BUILD
+@@ -0,0 +1,17 @@
++# Copyright lowRISC contributors (Sunburst project).
++# Licensed under the Apache License, Version 2.0, see LICENSE for details.
++# SPDX-License-Identifier: Apache-2.0
++
++load("@rules_python//python:defs.bzl", "py_library")
++
++package(default_visibility = ["//visibility:public"])
++
++py_library(
++    name = "ip",
++    srcs = ["ip.py"],
++)
++
++filegroup(
++    name = "tpl_files",
++    srcs = glob(["templates/*.tpl"]),
++)
+diff --git a/ip.py b/ip.py
+index 1c1b290..3cd102b 100644
+--- a/ip.py
++++ b/ip.py
+@@ -8,9 +8,9 @@
+
+ import hjson
+
++# This file is $REPO_TOP/hw/vendor/lowrisc_ip/util/make_new_dif/ip.py, so it takes six parent()
+-# This file is $REPO_TOP/util/make_new_dif/ip.py, so it takes three parent()
+ # calls to get back to the top.
++REPO_TOP = Path(__file__).resolve().parent.parent.parent.parent.parent.parent
+-REPO_TOP = Path(__file__).resolve().parent.parent.parent
+
+
+ class Alert:
+@@ -122,7 +122,7 @@
+             data_dir = REPO_TOP / "hw/top_earlgrey/ip/{0}/data/".format(
+                 self.name_snake)
+         else:
++            data_dir = REPO_TOP / "hw/vendor/lowrisc_ip/ip/{0}/data".format(self.name_snake)
+-            data_dir = REPO_TOP / "hw/ip/{0}/data".format(self.name_snake)
+         _hjson_file = data_dir / "{0}.hjson".format(self.name_snake)
+         with _hjson_file.open("r") as f:
+             _hjson_str = f.read()
+@@ -138,9 +138,13 @@
+         assert (self._hjson_data and
+                 "ERROR: must load IP HJSON before loading Alerts")
+         alerts = []
++        # By ignoring the alerts here we are able to generate DIF code that does not reference them
++        # but without shuffling all of the registers down. Changing the register offsets would
++        # create a software/hardware mismatch and require regeneration of the documentation.
++        #
++        # if "alert_list" in self._hjson_data:
++        #    for alert in self._hjson_data["alert_list"]:
++        #        alerts.append(Alert(alert))
+-        if "alert_list" in self._hjson_data:
+-            for alert in self._hjson_data["alert_list"]:
+-                alerts.append(Alert(alert))
+         return alerts
+
+     def _load_irqs(self):

hw/vendor/patches/lowrisc_ip/make_new_dif_py/0001_Repo_Structure.patch

@@ -0,0 +1,57 @@
+diff --git a/make_new_dif.py b/make_new_dif.py
+index b654fec..04c2e9f 100755
+--- a/make_new_dif.py
++++ b/make_new_dif.py
+@@ -48,9 +48,10 @@
+ from make_new_dif.ip import Ip
+ from mako.template import Template
+
++# This file is $IP_TOP/hw/vendor/lowrisc_ip/util/make_new_dif.py, so it takes five parent()
+-# This file is $REPO_TOP/util/make_new_dif.py, so it takes two parent()
+ # calls to get back to the top.
++IP_TOP = Path(__file__).resolve().parent.parent
++REPO_TOP = IP_TOP.parent.parent.parent
+-REPO_TOP = Path(__file__).resolve().parent.parent
+
+ ALL_PARTS = ["header", "checklist", "autogen"]
+
+@@ -95,12 +96,15 @@
+     try:
+         with open(topcfg_path, 'r') as ftop:
+             topcfg = hjson.load(ftop, use_decimal=True)
++        templated_modules = lib.get_templated_modules(topcfg)
++        ipgen_modules = lib.get_ipgen_modules(topcfg)
++        reggen_top_modules = lib.get_top_reggen_modules(topcfg)
+     except FileNotFoundError:
++        print(f"Warning: hjson {topcfg_path} could not be found")
++        templated_modules = []
++        ipgen_modules = []
++        reggen_top_modules = []
++    #    sys.exit(1)
+-        print(f"hjson {topcfg_path} could not be found")
+-        sys.exit(1)
+-    templated_modules = lib.get_templated_modules(topcfg)
+-    ipgen_modules = lib.get_ipgen_modules(topcfg)
+-    reggen_top_modules = lib.get_top_reggen_modules(topcfg)
+
+     # Check for regeneration mode (used in CI check:
+     # ci/scripts/check-generated.sh)
+@@ -137,7 +141,7 @@
+         autogen_dif_dir.mkdir(exist_ok=True)
+
+     # Render DIF templates.
++    template_path = IP_TOP / "util/make_new_dif/templates"
+-    template_path = REPO_TOP / "util/make_new_dif/templates"
+     for ip in ips:
+         if "header" in args.only:
+             header_template_file = template_path / "dif_template.h.tpl"
+@@ -178,8 +182,7 @@
+         # Format autogenerated file with clang-format.
+         try:
+             subprocess.check_call(
++                ["clang-format", "-i", "--"] + out_files)
+-                ["./bazelisk.sh", "run", "//quality:clang_format_fix", "--"] +
+-                out_files)
+         except subprocess.CalledProcessError:
+             logging.error(f"failed to format {out_file} with clang-format.")
+             sys.exit(1)

hw/vendor/patches/lowrisc_ip/spi_host/0005-Fix-DV.patch

@@ -20,8 +20,9 @@ index c582cda..dfa6796 100644
 @@ -155,7 +155,7 @@ package spi_host_env_pkg;
 
    // alerts
-   parameter uint NUM_ALERTS = 1;
+-  parameter uint NUM_ALERTS = 1;
 -  parameter string LIST_OF_ALERTS[] = {"fatal_fault"};
++  parameter uint NUM_ALERTS = 0;
 +  parameter string LIST_OF_ALERTS[] = {};
 
    // functions
@@ -46,7 +47,7 @@ index c27bc3f..aca0d8c 100644
 +                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
 +                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
 +                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/mem_tests.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
++                //"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
 +                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
 +                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                  //"{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson", // TODO(#18886): enable for V3
@@ -188,3 +189,16 @@ index dc4f409..4b9a89b 100644
 -  `ASSERT(Sd_I_A,  passthrough_i.passthrough_en -> passthrough_o.s == cio_sd_i, clk, !rst_n)
 -
  endmodule
+diff --git a/dv/env/seq_lib/spi_host_base_vseq.sv b/dv/env/seq_lib/spi_host_base_vseq.sv
+index e6dfc5f..90c3b33 100644
+--- a/dv/env/seq_lib/spi_host_base_vseq.sv
++++ b/dv/env/seq_lib/spi_host_base_vseq.sv
+@@ -114,7 +114,7 @@ class spi_host_base_vseq extends cip_base_vseq #(
+       end
+       [cfg.seq_cfg.host_spi_middle_clkdiv+1 : 16'hFFF] : cfg.csr_spinwait_timeout_ns *= 5;
+       [16'hFFF+1 : cfg.seq_cfg.host_spi_max_clkdiv] : cfg.csr_spinwait_timeout_ns *= 10;
+-      default : `uvm_fatal(`gfn, $sformatf("spi_config_regs.clkdiv[0]=0x%0x is out range"))
++      default : `uvm_fatal(`gfn, $sformatf("spi_config_regs.clkdiv[0]=0x%0x is out range", spi_config_regs.clkdiv[0]))
+     endcase
+   endfunction
+

hw/vendor/patches/lowrisc_ip/uart/0003-Fix-DV.patch

@@ -5,8 +5,9 @@ index aa029a0..095b54a 100644
 @@ -26,7 +26,7 @@ package uart_env_pkg;
    parameter uint MAX_TX_WATERMARK_LVL = 7;
    // alerts
-   parameter uint NUM_ALERTS = 1;
+-  parameter uint NUM_ALERTS = 1;
 -  parameter string LIST_OF_ALERTS[] = {"fatal_fault"};
++  parameter uint NUM_ALERTS = 0;
 +  parameter string LIST_OF_ALERTS[] = {};
 
    typedef enum int {
@@ -52,7 +53,7 @@ index 6d13daf..814b30a 100644
 -                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
 -                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]
 +                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
++                //"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
 +                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
 +                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson",
 +                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",

util/vendor.py

@@ -294,6 +294,8 @@ def make_default(have_patch_dir):
 
     @staticmethod
     def apply_patch(basedir, patchfile):
+        if os.path.isfile(basedir):
+            basedir = os.path.dirname(basedir)
         cmd = ['git', 'apply', '--directory', str(basedir), '-p1',
                str(patchfile)]
         if verbose: