[nrf fromlist] drivers: udc_dwc2: Workaround hibernation exit glitch #2459
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… Exit Programming Guide states that bit 17 on PCGCCTL writes should be set if the controller was enumerated for High Speed operation. Add the missing bit set to adhere to the Programming Guide. Upstream PR #: 85039 Signed-off-by: Tomasz Moń <[email protected]>
DWC2 otg versions earlier than 5.00a are subject to randomly occurring glitch on Hibernation Exit by Host Initiated Resume, Hibernation Exit by Device Inititated Resume and Hibernation Exit by Host Initiated Reset. When the glitch happens the device address is not correctly restored. If the address is not correctly restored then the tokens addressed to the device will timeout leading to host resetting the bus. Upstream PR #: 85039 Signed-off-by: Tomasz Moń <[email protected]>
tmon-nordic
added
the
backport v3.7.99-ncs3-branch
carlescufi
approved these changes
Feb 4, 2025
jfischer-no
approved these changes
Feb 4, 2025
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DWC2 otg versions earlier than 5.00a are subject to randomly occurring glitch on Hibernation Exit by Host Initiated Resume, Hibernation Exit by Device Inititated Resume and Hibernation Exit by Host Initiated Reset. When the glitch happens the device address is not correctly restored. If the address is not correctly restored then the tokens addressed to
the device will timeout leading to host resetting the bus.