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Backport 693769a~2..693769a from #2459.

… Exit

Programming Guide states that bit 17 on PCGCCTL writes should be set if
the controller was enumerated for High Speed operation. Add the missing
bit set to adhere to the Programming Guide.

Upstream PR #: 85039

Signed-off-by: Tomasz Moń <[email protected]>
(cherry picked from commit f25809c)
DWC2 otg versions earlier than 5.00a are subject to randomly occurring
glitch on Hibernation Exit by Host Initiated Resume, Hibernation Exit by
Device Inititated Resume and Hibernation Exit by Host Initiated Reset.
When the glitch happens the device address is not correctly restored.
If the address is not correctly restored then the tokens addressed to
the device will timeout leading to host resetting the bus.

Upstream PR #: 85039

Signed-off-by: Tomasz Moń <[email protected]>
(cherry picked from commit 693769a)
@tmon-nordic tmon-nordic merged commit 3b62269 into v3.7.99-ncs3-branch Feb 5, 2025
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4 participants