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ioctl: nvme_dsm use nvme_passthru_cmd directly #2

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ea5835a
ioctl: nvme_identify use nvme_passthru_cmd directly
igaw Jul 31, 2025
52926b4
ioctl: reorder nvme_get_log and nvme_get_log_page
igaw Jul 30, 2025
08703bb
ioctl: nvme_get_log use nvme_passthru_cmd directly
igaw Jul 29, 2025
0f642e1
ioctl: nvme_format_nvm use nvme_passthru_cmd directly
igaw Aug 1, 2025
58dedbd
ioctl: nvme_ns_mgmt use nvme_passthru_cmd directly
igaw Aug 1, 2025
e9e3621
ioctl: nvme_ns_attach use nvme_passthru_cmd directly
igaw Aug 1, 2025
763dc6a
ioctl: nvme_ns_download use nvme_passthru_cmd directly
igaw Aug 1, 2025
52bf56f
ioctl: nvme_fw_commit use nvme_passthru_cmd directly
igaw Aug 1, 2025
499a108
ioctl: nvme_security_send use nvme_passthru_cmd directly
igaw Aug 1, 2025
3876ec6
ioctl: nvme_dsm use nvme_passthru_cmd directly
ikegami-t Aug 2, 2025
812ebf2
ioctl: nvme_io use nvme_passthru_cmd directly
ikegami-t Aug 2, 2025
825164b
ioctl: add dsm and io commands dword fields
ikegami-t Aug 3, 2025
aa9c43f
ioctl: nvme_copy use nvme_passthru_cmd directly
ikegami-t Aug 4, 2025
04bc422
ioctl: reorder nsid argument
ikegami-t Aug 5, 2025
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91 changes: 72 additions & 19 deletions src/nvme/ioctl.h
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Original file line number Diff line number Diff line change
Expand Up @@ -335,6 +335,59 @@ enum nvme_cmd_dword_fields {
NVME_DSM_CDW11_IDW_MASK = 0x1,
NVME_DSM_CDW11_AD_SHIFT = 2,
NVME_DSM_CDW11_AD_MASK = 0x1,
NVME_DSM_CDW11_ATTRS_SHIFT = NVME_DSM_CDW11_IDR_SHIFT,
NVME_DSM_CDW11_ATTRS_MASK = NVME_VAL(DSM_CDW11_IDR) |
NVME_VAL(DSM_CDW11_IDW) |
NVME_VAL(DSM_CDW11_AD),
NVME_NVM_CDW2_ELBTU_SHIFT = 0,
NVME_NVM_CDW2_ELBTU_MASK = 0xffff,
NVME_NVM_CDW3_ELBTU_SHIFT = 0,
NVME_NVM_CDW3_ELBTU_MASK = 0xffffffff,
NVME_NVM_CDW10_SLBAL_SHIFT = 0,
NVME_NVM_CDW10_SLBAL_MASK = 0xffffffff,
NVME_NVM_CDW11_SLBAU_SHIFT = 0,
NVME_NVM_CDW11_SLBAU_MASK = 0xffffffff,
NVME_NVM_CDW12_NLB_SHIFT = 0,
NVME_NVM_CDW12_NLB_MASK = 0xffff,
NVME_NVM_CDW12_CETYPE_SHIFT = 16,
NVME_NVM_CDW12_CETYPE_MASK = 0xf,
NVME_NVM_CDW12_STC_SHIFT = 24,
NVME_NVM_CDW12_STC_MASK = 0x1,
NVME_NVM_CDW12_PRINFO_SHIFT = 26,
NVME_NVM_CDW12_PRINFO_MASK = 0xf,
NVME_NVM_CDW12_FUA_SHIFT = 30,
NVME_NVM_CDW12_FUA_MASK = 0x1,
NVME_NVM_CDW12_LR_SHIFT = 31,
NVME_NVM_CDW12_LR_MASK = 0x1,
NVME_NVM_CDW12_CONTROL_SHIFT = NVME_NVM_CDW12_CETYPE_SHIFT,
NVME_NVM_CDW12_CONTROL_MASK = NVME_VAL(NVM_CDW12_CETYPE) |
NVME_VAL(NVM_CDW12_STC) |
NVME_VAL(NVM_CDW12_PRINFO) |
NVME_VAL(NVM_CDW12_FUA) |
NVME_VAL(NVM_CDW12_LR),
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@igaw igaw Aug 8, 2025

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btw, this masks is already shifted thus it doesn't work as expected. I've added the necessary >> NVME_NVM_CDW12_CONTROL_SHIFT so it works. Caught by meson test -C .build :)

NVME_NVM_CDW13_DSM_AF_SHIFT = 0,
NVME_NVM_CDW13_DSM_AF_MASK = 0xf,
NVME_NVM_CDW13_DSM_AL_SHIFT = 4,
NVME_NVM_CDW13_DSM_AL_MASK = 0x3,
NVME_NVM_CDW13_DSM_SEQREQ_SHIFT = 6,
NVME_NVM_CDW13_DSM_SEQREQ_MASK = 0x1,
NVME_NVM_CDW13_DSM_INCPRS_SHIFT = 7,
NVME_NVM_CDW13_DSM_INCPRS_MASK = 0x1,
NVME_NVM_CDW13_DSM_SHIFT = NVME_NVM_CDW13_DSM_AF_SHIFT,
NVME_NVM_CDW13_DSM_MASK = NVME_VAL(NVM_CDW13_DSM_AF) |
NVME_VAL(NVM_CDW13_DSM_AL) |
NVME_VAL(NVM_CDW13_DSM_SEQREQ) |
NVME_VAL(NVM_CDW13_DSM_INCPRS),
NVME_NVM_CDW13_CEV_AF_SHIFT = 0,
NVME_NVM_CDW13_CEV_AF_MASK = 0xffff,
NVME_NVM_CDW13_DSPEC_SHIFT = 16,
NVME_NVM_CDW13_DSPEC_MASK = 0xffff,
NVME_NVM_CDW14_ELBTL_SHIFT = 0,
NVME_NVM_CDW14_ELBTL_MASK = 0xffffffff,
NVME_NVM_CDW15_ELBAT_SHIFT = 0,
NVME_NVM_CDW15_ELBAT_MASK = 0xffff,
NVME_NVM_CDW15_ELBATM_SHIFT = 16,
NVME_NVM_CDW15_ELBATM_MASK = 0xffff,
};

/**
Expand Down Expand Up @@ -3709,27 +3762,27 @@ static inline int nvme_set_var_size_tags(__u32 *cmd_dw2, __u32 *cmd_dw3, __u32 *

switch (pif) {
case NVME_NVM_PIF_16B_GUARD:
cdw14 = reftag & 0xffffffff;
cdw14 |= ((storage_tag << (32 - sts)) & 0xffffffff);
cdw14 = NVME_SET(reftag, NVM_CDW14_ELBTL);
cdw14 |= NVME_SET(storage_tag << (32 - sts), NVM_CDW14_ELBTL);
break;
case NVME_NVM_PIF_32B_GUARD:
cdw14 = reftag & 0xffffffff;
cdw3 = reftag >> 32;
cdw14 |= ((storage_tag << (80 - sts)) & 0xffff0000);
cdw14 = NVME_SET(reftag, NVM_CDW14_ELBTL);
cdw3 = NVME_SET(reftag >> 32, NVM_CDW3_ELBTU);
cdw14 |= NVME_SET((storage_tag << (80 - sts)) & 0xffff0000, NVM_CDW14_ELBTL);
if (sts >= 48)
cdw3 |= ((storage_tag >> (sts - 48)) & 0xffffffff);
cdw3 |= NVME_SET(storage_tag >> (sts - 48), NVM_CDW3_ELBTU);
else
cdw3 |= ((storage_tag << (48 - sts)) & 0xffffffff);
cdw2 = (storage_tag >> (sts - 16)) & 0xffff;
cdw3 |= NVME_SET(storage_tag << (48 - sts), NVM_CDW3_ELBTU);
cdw2 = NVME_SET(storage_tag >> (sts - 16), NVM_CDW2_ELBTU);
break;
case NVME_NVM_PIF_64B_GUARD:
cdw14 = reftag & 0xffffffff;
cdw3 = (reftag >> 32) & 0xffff;
cdw14 |= ((storage_tag << (48 - sts)) & 0xffffffff);
cdw14 = NVME_SET(reftag, NVM_CDW14_ELBTL);
cdw3 = NVME_SET((reftag >> 32) & 0xffff, NVM_CDW3_ELBTU);
cdw14 |= NVME_SET(storage_tag << (48 - sts), NVM_CDW14_ELBTL);
if (sts >= 16)
cdw3 |= ((storage_tag >> (sts - 16)) & 0xffff);
cdw3 |= NVME_SET((storage_tag >> (sts - 16)) & 0xffff, NVM_CDW3_ELBTU);
else
cdw3 |= ((storage_tag << (16 - sts)) & 0xffff);
cdw3 |= NVME_SET((storage_tag << (16 - sts)) & 0xffff, NVM_CDW3_ELBTU);
break;
default:
perror("Unsupported Protection Information Format");
Expand Down Expand Up @@ -3788,11 +3841,11 @@ static inline int nvme_io(nvme_link_t l, __u8 opcode, __u64 slba, __u64 storage_
__u16 dspec, __u8 dsm, __u64 reftag_u64, __u8 sts, __u8 pif,
__u32 *result)
{
__u32 cdw10 = slba & 0xffffffff;
__u32 cdw11 = slba >> 32;
__u32 cdw12 = nlb | (control << 16);
__u32 cdw13 = dsm | (dspec << 16);
__u32 cdw15 = apptag | (appmask << 16);
__u32 cdw10 = NVME_SET(slba, NVM_CDW10_SLBAL);
__u32 cdw11 = NVME_SET(slba >> 32, NVM_CDW11_SLBAU);
__u32 cdw12 = NVME_SET(nlb, NVM_CDW12_NLB) | NVME_SET(control, NVM_CDW12_CONTROL);
__u32 cdw13 = NVME_SET(dsm, NVM_CDW13_DSM) | NVME_SET(dspec, NVM_CDW13_DSPEC);
__u32 cdw15 = NVME_SET(apptag, NVM_CDW15_ELBAT) | NVME_SET(appmask, NVM_CDW15_ELBATM);

struct nvme_passthru_cmd cmd = {
.opcode = opcode,
Expand Down Expand Up @@ -4152,7 +4205,7 @@ static inline int nvme_dsm(nvme_link_t l, struct nvme_dsm_range *dsm, __u16 nr_r
__u32 nsid, __u32 *result)
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@igaw igaw Aug 5, 2025 •
edited
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As I just figured out, the nsid is in cdw0, so it should be right after nvme_link_t l. Sorry for my mistake.

{
__u32 cdw10 = NVME_SET(nr_ranges - 1, DSM_CDW10_NR);
__u32 cdw11 = attrs;
__u32 cdw11 = NVME_SET(attrs, DSM_CDW11_ATTRS);

struct nvme_passthru_cmd cmd = {
.opcode = nvme_cmd_dsm,
Expand Down