os-fpga · behzadmehmood · Oct 18, 2024 · Oct 2, 2024 · Oct 2, 2024 · Oct 7, 2024
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -17,7 +17,7 @@ set(VERSION_MINOR 0)
 
 
 
-set(VERSION_PATCH 378)
+set(VERSION_PATCH 379)
 
 
 

diff --git a/design_edit/Makefile b/design_edit/Makefile
@@ -67,7 +67,7 @@ VERILOG_MODULES	= $(COMMON)/cells_sim.v \
 				  $(GENESIS3)/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v
 
 NAME = design-edit
-SOURCES = src/primitives_extractor.cc src/rs_design_edit.cc
+SOURCES = src/primitives_extractor.cc src/rs_design_edit.cc src/netlist_checker.cc
 
 OBJS := $(SOURCES:cc=o)
 

diff --git a/design_edit/Tests/GJC-1/GJC-1.ys b/design_edit/Tests/GJC-1/GJC-1.ys
diff --git a/design_edit/Tests/GJC-1/flop2flop.sdc b/design_edit/Tests/GJC-1/flop2flop.sdc
diff --git a/design_edit/Tests/GJC-1/flop2flop.v b/design_edit/Tests/GJC-1/flop2flop.v
diff --git a/design_edit/Tests/GJC-1/gold/flop2flop_post_synth.eblif b/design_edit/Tests/GJC-1/gold/flop2flop_post_synth.eblif
diff --git a/design_edit/Tests/GJC-1/gold/flop2flop_post_synth.v b/design_edit/Tests/GJC-1/gold/flop2flop_post_synth.v
diff --git a/design_edit/Tests/GJC-1/gold/io_config.json b/design_edit/Tests/GJC-1/gold/io_config.json
diff --git a/design_edit/Tests/GJC-1/gold/wrapper_flop2flop_post_synth.eblif b/design_edit/Tests/GJC-1/gold/wrapper_flop2flop_post_synth.eblif
diff --git a/design_edit/Tests/GJC-1/gold/wrapper_flop2flop_post_synth.v b/design_edit/Tests/GJC-1/gold/wrapper_flop2flop_post_synth.v
Original file line number	Diff line number	Diff line change
Expand Up		@@ -17,7 +17,7 @@ set(VERSION_MINOR 0)



		set(VERSION_PATCH 378)
		set(VERSION_PATCH 379)



Expand Down