Adding Support for the arty z7 20 and zybo z7 20 fpga boards

[Xelef2000]

I want to add support for the Arty Z7 20 FPGA board.
This PR adds the constraints, adjusts the build script, and the top module.

I couldn't test the modified build script with the genesys2 since I do not have one.

[phsauter]

Quick update: I am planning to test your FPGA configurations in the next two weeks on all three boards.

[Xelef2000]

It looks like the rebase on croc 1.1 broke the FPGA synthesis.

ERROR: [Synth 8-11216] the number of actual arguments '3' differs from the number of formal arguments '2' for macro 'ASSERT_INIT' [/home/felix/Documents/Projects/FPGA/vlsi2/croc/rtl/common_cells/fifo_v3.sv:143]
ERROR: [Synth 8-10939] macro 'ASSERT_INIT' is defined here [/home/felix/Documents/Projects/FPGA/vlsi2/croc/rtl/cve2/include/lowrisc_prim/prim_assert_dummy_macros.svh:10]
ERROR: [Synth 8-11216] the number of actual arguments '5' differs from the number of formal arguments '4' for macro 'ASSERT' [/home/felix/Documents/Projects/FPGA/vlsi2/croc/rtl/common_cells/fifo_v3.sv:146]
ERROR: [Synth 8-10939] macro 'ASSERT' is defined here [/home/felix/Documents/Projects/FPGA/vlsi2/croc/rtl/cve2/include/lowrisc_prim/prim_assert_dummy_macros.svh:13]
ERROR: [Synth 8-11216] the number of actual arguments '5' differs from the number of formal arguments '4' for macro 'ASSERT' [/home/felix/Documents/Projects/FPGA/vlsi2/croc/rtl/common_cells/fifo_v3.sv:149]
ERROR: [Synth 8-439] module 'croc_xilinx' not found

[Xelef2000]

the last commit should fix the issue