Towards complete pulpv3 coverage #8
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p.ror had only one source register but according to the docs it has two
Different implementations have edited the encoding file directly instead of generating it, this has caused diverging definitions of the addresses used. The current default are the PULPv3 addresses that completely avoid any known conflicts. Other options are included but commented-out for the sake of documentation and completeness.
Technically partmac is not a pseudo and it should be possible to use it independently.
This was referenced Jun 21, 2023
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Adds opcode definitions that cover almost all instructions in pulpv3 (elw is missing).
This was done as a SoCDAML miniproject in summer 2022.
The entire project consists of changes to:
pulp-platform/riscv-opcodes
pulp-platform/riscv-isa-sim#3
pulp-platform/riscv-tests#5
All are necessary for the goal of having definitions (riscv-opcodes), a reference (riscv-isa-sim) and tests (risv-tests) for the pulpv3 instruction set.
Attached is a slide from the presentation of the project, it shows which instructions were added.
presentation.pdf