Towards complete pulpv3 coverage

README.md

@@ -47,3 +47,27 @@ Ariane and Snitch do not use the same FPU configuration.
 There might be some overlap in opcodes between extensions. These are noted as far as known
 in the corresponding files. In some cases these overlaps can be avoided by making one of the
 opcodes a pseudo-opcodes using `@` in front.
+
+## Control and Status Registers
+
+### HW-Loop Register Collisions
+
+There are three existing address spaces for the HW-Loop [CSRs defined in binutils](https://iis-git.ee.ethz.ch/gnu/riscv-binutils-gdb/-/blob/riscv-binutils-2.34-pulp/include/opcode/riscv-opc.h#L829), all of them have collisions.
+The default configuration uses the CV32E40P addresses.
+
+#### CV32E40P
+
+The addresses 0x800-0x802 and 0x804-0x806 are used, this collides with the fmode CSR used in Snitch.
+The source of the HW-Loop addresses: https://cv32e40p.readthedocs.io/en/latest/control_status_registers/
+The [offending riscv-opcodes commit](https://github.com/pulp-platform/riscv-opcodes/commit/1e5fa7787b4e388c51956f6e7fd26d4d249a7d80) that adds the collisions from Snitch: (file parse_opcodes, line 124)
+
+#### PULPv3
+
+The addresses 0x7C0 - 0x7C2 and 0x7C4-0x7C6 are used, this collides with the ssr and fpmode CSRs used in Snitch.
+The [offending riscv-opcodes commit](https://github.com/pulp-platform/riscv-opcodes/commit/1e5fa7787b4e388c51956f6e7fd26d4d249a7d80) that adds the collisions from Snitch: (file parse_opcodes, line 133-134)
+
+#### PULPv1
+
+The addresses 0x7B0 - 0x7B2 and 0x7B4-0x7B6 are used, this collides with the debug mode registers (dcsr, dpc, dscratch0) from the official spec (page 11 in [RISCV priviliged v1.12](https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf)).
+There is no reason to use this for anything new, it is considered DEPRECATED.
+

config.mk

@@ -2,12 +2,40 @@
 
 # RV32IMA := opcodes-rv32i opcodes-rv32m opcodes-rv32a opcodes-system
 
-# Xpulpimg
-RV32XPULPIMG := opcodes-xpulpabs_CUSTOM opcodes-xpulpbr_CUSTOM opcodes-xpulpclip_CUSTOM opcodes-xpulpmacsi_CUSTOM opcodes-xpulpminmax_CUSTOM opcodes-xpulpslet_CUSTOM opcodes-xpulpvect_CUSTOM opcodes-xpulpvectshufflepack_CUSTOM
+# XPULPIMG
+# Branching
+RV32XPULPIMG := opcodes-xpulpbr_CUSTOM 
+RV32XPULPIMG += opcodes-xpulphwloop_CUSTOM
+
+# Comparison
+RV32XPULPIMG += opcodes-xpulpslet_CUSTOM
+
+# Bit Twiddle
 RV32XPULPIMG += opcodes-xpulpbitop_CUSTOM
+RV32XPULPIMG += opcodes-xpulbitrev_CUSTOM
 # RV32XPULPIMG += opcodes-xpulpbitopsmall_CUSTOM #is a subset of opcodes-xpulpbitop_CUSTOM
+
+# Load/Store
 # RV32XPULPIMG += opcodes-xpulppostmod_CUSTOM #conflict with opcodes-ssr_CUSTOM
 
+# Arithmetic
+RV32XPULPIMG += opcodes-xpulpabs_CUSTOM
+RV32XPULPIMG += opcodes-xpulpclip_CUSTOM
+RV32XPULPIMG += opcodes-xpulpminmax_CUSTOM
+RV32XPULPIMG += opcodes-xpulpmacsi_CUSTOM
+RV32XPULPIMG += opcodes-xpulppartmac_CUSTOM # subset of xpulpmacrnhi (declared as pseudo instructions)
+
+# Arithmetic with round and norm
+RV32XPULPIMG += opcodes-xpulpaddsubrn_CUSTOM
+RV32XPULPIMG += opcodes-xpulpmulrnhi_CUSTOM
+RV32XPULPIMG += opcodes-xpulpmacrnhi_CUSTOM
+
+# Packed SIMD
+RV32XPULPIMG += opcodes-xpulpvect_CUSTOM
+RV32XPULPIMG += opcodes-xpulpvectcomplex_CUSTOM
+RV32XPULPIMG += opcodes-xpulpvectshufflepack_CUSTOM
+
+
 # Snitch
 SNITCH_OPCODES := opcodes-dma_CUSTOM opcodes-frep_CUSTOM opcodes-ssr_CUSTOM
 

opcodes-xpulbitrev_CUSTOM

@@ -0,0 +1,15 @@
+# Xpulp extension subset: bit reverse operation
+
+# format of a line in this file:
+# <instruction name> <args> <opcode>
+#
+# <opcode> is given by specifying one or more range/value pairs:
+# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0)
+#
+# <args> is one of rd, rs1, rs2, rs3, aqrl, fm, pred, succ, rm,
+# funct3, imm20, jimm20, imm12, imm12hi, bimm12hi, imm12lo,
+# bimm12lo, zimm, shamt, shamtw, imm5, imm6, vd, vs3, vs1, vs2,
+# vm, wd, amoop, nf, simm5, zimm11, prs3, L, uimms, Luimm5, Luimm2
+# vseglen, stagger_max, stagger_mask
+
+p.bitrev    rd rs1 Luimm2 imm5   31..30=3 29..27=0 14..12=5 6..2=0x0C 1..0=3

opcodes-xpulpaddsubrn_CUSTOM

@@ -0,0 +1,31 @@
+# Xpulp extension subset: addition/subtraction with round and norm operations
+
+# format of a line in this file:
+# <instruction name> <args> <opcode>
+#
+# <opcode> is given by specifying one or more range/value pairs:
+# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0)
+#
+# <args> is one of rd, rs1, rs2, rs3, aqrl, fm, pred, succ, rm,
+# funct3, imm20, jimm20, imm12, imm12hi, bimm12hi, imm12lo,
+# bimm12lo, zimm, shamt, shamtw, imm5, imm6, vd, vs3, vs1, vs2,
+# vm, wd, amoop, nf, simm5, zimm11, prs3, L, uimms, Luimm5,
+# vseglen, stagger_max, stagger_mask
+
+p.addN   	rd rs1 rs2 Luimm5   31..30=0 14..12=2 6..2=0x16 1..0=3
+p.adduN   	rd rs1 rs2 Luimm5   31..30=2 14..12=2 6..2=0x16 1..0=3
+p.addRN   	rd rs1 rs2 Luimm5   31..30=0 14..12=6 6..2=0x16 1..0=3
+p.adduRN   	rd rs1 rs2 Luimm5   31..30=2 14..12=6 6..2=0x16 1..0=3
+p.subN   	rd rs1 rs2 Luimm5   31..30=0 14..12=3 6..2=0x16 1..0=3
+p.subuN   	rd rs1 rs2 Luimm5   31..30=2 14..12=3 6..2=0x16 1..0=3
+p.subRN   	rd rs1 rs2 Luimm5   31..30=0 14..12=7 6..2=0x16 1..0=3
+p.subuRN   	rd rs1 rs2 Luimm5   31..30=2 14..12=7 6..2=0x16 1..0=3
+
+p.addNr   	rd rs1 rs2 31..30=1 29..25=0 14..12=2 6..2=0x16 1..0=3
+p.adduNr   	rd rs1 rs2 31..30=3 29..25=0 14..12=2 6..2=0x16 1..0=3
+p.addRNr   	rd rs1 rs2 31..30=1 29..25=0 14..12=6 6..2=0x16 1..0=3
+p.adduRNr   rd rs1 rs2 31..30=3 29..25=0 14..12=6 6..2=0x16 1..0=3
+p.subNr   	rd rs1 rs2 31..30=1 29..25=0 14..12=3 6..2=0x16 1..0=3
+p.subuNr   	rd rs1 rs2 31..30=3 29..25=0 14..12=3 6..2=0x16 1..0=3
+p.subRNr   	rd rs1 rs2 31..30=1 29..25=0 14..12=7 6..2=0x16 1..0=3
+p.subuRNr  	rd rs1 rs2 31..30=3 29..25=0 14..12=7 6..2=0x16 1..0=3

opcodes-xpulpbitop_CUSTOM

@@ -31,8 +31,8 @@ p.bsetr      rd rs1 rs2  31..30=2 29..25=0 14..12=4 6..2=0x0C 1..0=3
 p.bclr       rd rs1 Luimm5 imm5   31..30=3 14..12=3 6..2=0x0C 1..0=3
 p.bclrr      rd rs1 rs2  31..30=2 29..25=0 14..12=3 6..2=0x0C 1..0=3
 
-p.cnt    rd rs1 rs2  31..25=8           14..12=3 6..2=0x0C 1..0=3
-p.clb    rd rs1      31..25=8  24..20=0 14..12=2 6..2=0x0C 1..0=3
-p.fl1    rd rs1      31..25=8  24..20=0 14..12=1 6..2=0x0C 1..0=3
+p.ror    rd rs1 rs2  31..25=4           14..12=5 6..2=0x0C 1..0=3
 p.ff1    rd rs1      31..25=8  24..20=0 14..12=0 6..2=0x0C 1..0=3
-p.ror    rd rs1      31..25=4  24..20=0 14..12=5 6..2=0x0C 1..0=3
+p.fl1    rd rs1      31..25=8  24..20=0 14..12=1 6..2=0x0C 1..0=3
+p.clb    rd rs1      31..25=8  24..20=0 14..12=2 6..2=0x0C 1..0=3
+p.cnt    rd rs1      31..25=8  24..20=0 14..12=3 6..2=0x0C 1..0=3

opcodes-xpulphwloop_CUSTOM

@@ -16,7 +16,7 @@
 
 lp.starti   L imm12               19..15=0 14..12=0 11..8=0 6..2=0x1E 1..0=3
 lp.endi     L imm12               19..15=0 14..12=1 11..8=0 6..2=0x1E 1..0=3
-lp.count    L rs1                 31..20=0 14..12=2 11..8=0 6..2=0x1E 1..0=3
+lp.count    L rs1        31..20=0 				 14..12=2 11..8=0 6..2=0x1E 1..0=3
 lp.counti   L imm12               19..15=0 14..12=3 11..8=0 6..2=0x1E 1..0=3
-lp.setup    L rs1 imm12           14..12=4 11..8=0 6..2=0x1E 1..0=3
-lp.setupi   L imm12 uimms         14..12=5 11..8=0 6..2=0x1E 1..0=3
+lp.setup    L rs1 imm12           				 14..12=4 11..8=0 6..2=0x1E 1..0=3
+lp.setupi   L imm12 uimms         				 14..12=5 11..8=0 6..2=0x1E 1..0=3

opcodes-xpulpmacrnhi_CUSTOM

@@ -0,0 +1,23 @@
+# Xpulp extension subset: 16x16->32bit MAC with round and norm operations
+
+# format of a line in this file:
+# <instruction name> <args> <opcode>
+#
+# <opcode> is given by specifying one or more range/value pairs:
+# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0)
+#
+# <args> is one of rd, rs1, rs2, rs3, aqrl, fm, pred, succ, rm,
+# funct3, imm20, jimm20, imm12, imm12hi, bimm12hi, imm12lo,
+# bimm12lo, zimm, shamt, shamtw, imm5, imm6, vd, vs3, vs1, vs2,
+# vm, wd, amoop, nf, simm5, zimm11, prs3, L, uimms, Luimm5,
+# vseglen, stagger_max, stagger_mask
+
+# rs3 is rd hence it does not appear here
+p.macuN     rd rs1 rs2 Luimm5   31..30=0 14..12=1 6..2=0x16 1..0=3
+p.machhuN   rd rs1 rs2 Luimm5   31..30=1 14..12=1 6..2=0x16 1..0=3
+p.macsN     rd rs1 rs2 Luimm5   31..30=2 14..12=1 6..2=0x16 1..0=3
+p.machhsN   rd rs1 rs2 Luimm5   31..30=3 14..12=1 6..2=0x16 1..0=3
+p.macsRN    rd rs1 rs2 Luimm5   31..30=2 14..12=5 6..2=0x16 1..0=3
+p.machhsRN  rd rs1 rs2 Luimm5   31..30=3 14..12=5 6..2=0x16 1..0=3
+p.macuRN    rd rs1 rs2 Luimm5   31..30=0 14..12=5 6..2=0x16 1..0=3
+p.machhuRN  rd rs1 rs2 Luimm5   31..30=1 14..12=5 6..2=0x16 1..0=3

opcodes-xpulpminmax_CUSTOM

@@ -18,6 +18,8 @@ p.min    rd rs1 rs2  31..25=2           14..12=4 6..2=0x0C 1..0=3
 p.minu   rd rs1 rs2  31..25=2           14..12=5 6..2=0x0C 1..0=3
 p.max    rd rs1 rs2  31..25=2           14..12=6 6..2=0x0C 1..0=3
 p.maxu   rd rs1 rs2  31..25=2           14..12=7 6..2=0x0C 1..0=3
-# might be missing p.avg, p.avgu respectively p.addN, p.adduN
-p.addN   rd rs1 rs2  31..30=0 Luimm5 14..12=2 6..2=0x16 1..0=3
-p.adduN  rd rs1 rs2  31..30=2 Luimm5 14..12=2 6..2=0x16 1..0=3
+
+# pulp >= v2: p.addN, p.adduN in addsubrn replaces p.avg, p.avgu
+# -> pseudo op for compatibility
+@p.avg   rd rs1 rs2  31..30=0  Luimm5 	14..12=2 6..2=0x16 1..0=3
+@p.avgu  rd rs1 rs2  31..30=2  Luimm5 	14..12=2 6..2=0x16 1..0=3

opcodes-xpulpmulrnhi_CUSTOM

@@ -0,0 +1,27 @@
+# Xpulp extension subset: 16x16->32bit MUL with round and norm operations
+
+# format of a line in this file:
+# <instruction name> <args> <opcode>
+#
+# <opcode> is given by specifying one or more range/value pairs:
+# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0)
+#
+# <args> is one of rd, rs1, rs2, rs3, aqrl, fm, pred, succ, rm,
+# funct3, imm20, jimm20, imm12, imm12hi, bimm12hi, imm12lo,
+# bimm12lo, zimm, shamt, shamtw, imm5, imm6, vd, vs3, vs1, vs2,
+# vm, wd, amoop, nf, simm5, zimm11, prs3, L, uimms, Luimm5,
+# vseglen, stagger_max, stagger_mask
+
+p.muluN     rd rs1 rs2 Luimm5   31..30=0 14..12=0 6..2=0x16 1..0=3
+p.mulhhuN   rd rs1 rs2 Luimm5   31..30=1 14..12=0 6..2=0x16 1..0=3
+p.mulsN     rd rs1 rs2 Luimm5   31..30=2 14..12=0 6..2=0x16 1..0=3
+p.mulhhsN   rd rs1 rs2 Luimm5   31..30=3 14..12=0 6..2=0x16 1..0=3
+p.muluRN    rd rs1 rs2 Luimm5   31..30=0 14..12=4 6..2=0x16 1..0=3
+p.mulhhuRN  rd rs1 rs2 Luimm5   31..30=1 14..12=4 6..2=0x16 1..0=3
+p.mulsRN    rd rs1 rs2 Luimm5   31..30=2 14..12=4 6..2=0x16 1..0=3
+p.mulhhsRN  rd rs1 rs2 Luimm5   31..30=3 14..12=4 6..2=0x16 1..0=3
+
+@p.mulu     rd rs1 rs2 31..30=0 29..25=0 14..12=0 6..2=0x16 1..0=3
+@p.mulhhu   rd rs1 rs2 31..30=1 29..25=0 14..12=0 6..2=0x16 1..0=3
+@p.muls     rd rs1 rs2 31..30=2 29..25=0 14..12=0 6..2=0x16 1..0=3
+@p.mulhhs   rd rs1 rs2 31..30=3 29..25=0 14..12=0 6..2=0x16 1..0=3

opcodes-xpulppartmac_CUSTOM

@@ -0,0 +1,19 @@
+# Xpulp extension subset: 16x16->32bit MAC (pseudo of macrnhi)
+
+# format of a line in this file:
+# <instruction name> <args> <opcode>
+#
+# <opcode> is given by specifying one or more range/value pairs:
+# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0)
+#
+# <args> is one of rd, rs1, rs2, rs3, aqrl, fm, pred, succ, rm,
+# funct3, imm20, jimm20, imm12, imm12hi, bimm12hi, imm12lo,
+# bimm12lo, zimm, shamt, shamtw, imm5, imm6, vd, vs3, vs1, vs2,
+# vm, wd, amoop, nf, simm5, zimm11, prs3, L, uimms, Luimm5,
+# vseglen, stagger_max, stagger_mask
+
+# remove '@' if xpulpmacrnhi is not in use
+@p.macu     rd rs1 rs2   31..30=0 29..25=0 14..12=1 6..2=0x16 1..0=3
+@p.machhu   rd rs1 rs2   31..30=1 29..25=0 14..12=1 6..2=0x16 1..0=3
+@p.macs     rd rs1 rs2   31..30=2 29..25=0 14..12=1 6..2=0x16 1..0=3
+@p.machhs   rd rs1 rs2   31..30=3 29..25=0 14..12=1 6..2=0x16 1..0=3

opcodes-xpulpvectcomplex_CUSTOM

@@ -0,0 +1,31 @@
+# Xpulp extension subset: SIMD complex operations with format: (16bit imag, 16bit real)
+# and SIMD comparison operations
+
+# format of a line in this file:
+# <instruction name> <args> <opcode>
+#
+# <opcode> is given by specifying one or more range/value pairs:
+# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0)
+#
+# <args> is one of rd, rs1, rs2, rs3, aqrl, fm, pred, succ, rm,
+# funct3, imm20, jimm20, imm12, imm12hi, bimm12hi, imm12lo,
+# bimm12lo, zimm, shamt, shamtw, imm5, imm6, vd, vs3, vs1, vs2,
+# vm, wd, amoop, nf, simm5, zimm11, prs3, L, uimms, Luimm5,
+# vseglen, stagger_max, stagger_mask
+
+pv.cplxconj.h           rd rs1      31..27=0x0b 26=1 25=0 24..20=0  14..12=0 6..2=0x15 1..0=3
+
+pv.subrotmj.h           rd rs1 rs2  31..27=0x0d 26=1 25=0           14..12=0 6..2=0x15 1..0=3
+pv.subrotmj.h.div2      rd rs1 rs2  31..27=0x0d 26=1 25=0           14..12=2 6..2=0x15 1..0=3
+pv.subrotmj.h.div4      rd rs1 rs2  31..27=0x0d 26=1 25=0           14..12=4 6..2=0x15 1..0=3
+pv.subrotmj.h.div8      rd rs1 rs2  31..27=0x0d 26=1 25=0           14..12=6 6..2=0x15 1..0=3
+
+pv.cplxmul.h.r          rd rs1 rs2  31..27=0x0a 26=1 25=0           14..12=0 6..2=0x15 1..0=3
+pv.cplxmul.h.r.div2     rd rs1 rs2  31..27=0x0a 26=1 25=0           14..12=2 6..2=0x15 1..0=3
+pv.cplxmul.h.r.div4     rd rs1 rs2  31..27=0x0a 26=1 25=0           14..12=4 6..2=0x15 1..0=3
+pv.cplxmul.h.r.div8     rd rs1 rs2  31..27=0x0a 26=1 25=0           14..12=6 6..2=0x15 1..0=3
+
+pv.cplxmul.h.i          rd rs1 rs2  31..27=0x0a 26=1 25=1           14..12=0 6..2=0x15 1..0=3
+pv.cplxmul.h.i.div2     rd rs1 rs2  31..27=0x0a 26=1 25=1           14..12=2 6..2=0x15 1..0=3
+pv.cplxmul.h.i.div4     rd rs1 rs2  31..27=0x0a 26=1 25=1           14..12=4 6..2=0x15 1..0=3
+pv.cplxmul.h.i.div8     rd rs1 rs2  31..27=0x0a 26=1 25=1           14..12=6 6..2=0x15 1..0=3

parse_opcodes

@@ -55,6 +55,7 @@ arglut['prs3'] = (11,7)
 arglut['L'] = (7,7)
 arglut['uimms'] = (19,15)
 arglut['Luimm5'] = (29,25)
+arglut['Luimm2'] = (26,25)
 arglut['vseglen'] = (31,29)
 arglut['stagger_max'] = (14,12)
 arglut['stagger_mask'] = (11,8)
@@ -123,8 +124,38 @@ csrs = [
   (0x043, 'utval'),
   (0x044, 'uip'),
 
-  # Custom User R/W
-  (0x800, 'fmode'),
+  # Custom User R/W Snitch
+  # Removed due to collisions with HW Loop
+  # Todo: Find a better solution
+  # (0x800, 'fmode'),
+
+  # Custom User R/W Xpulp
+  # HW Loop as defined by CV32E40P
+  # Collides with Snitch CSRs, namely fmode at 0x800
+  (0x800, 'lpstart0'),
+  (0x801, 'lpend0'),
+  (0x802, 'lpcount0'),
+  (0x804, 'lpstart1'),
+  (0x805, 'lpend1'),
+  (0x806, 'lpcount1'),
+
+  # HW Loop Registers for PULPv3
+  # Collides with Snitch CSRs, namely ssr and fpmode at 0x7C0-0x7C1
+  # (0x7C0, 'lpstart0'),
+  # (0x7C1, 'lpend0'),
+  # (0x7C2, 'lpcount0'),
+  # (0x7C4, 'lpstart1'),
+  # (0x7C5, 'lpend1'),
+  # (0x7C6, 'lpcount1'),
+
+  # HW Loop for PULPv1, DO NOT USE
+  # Collides with debug mode regs (dcsr, dpc, dscratch)
+  # (0x7B0, 'lpstart0'),
+  # (0x7B1, 'lpend0'),
+  # (0x7B2, 'lpcount0'),
+  # (0x7B4, 'lpstart1'),
+  # (0x7B5, 'lpend1'),
+  # (0x7B6, 'lpcount1'),
 
   # Standard User RO
   (0xC00, 'cycle'),