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Output VCD file compliant with the standard #291

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Output VCD file compliant with the standard #291

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4 changes: 4 additions & 0 deletions pymtl3/datatypes/PythonBits.py
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Original file line number Diff line number Diff line change
Expand Up @@ -529,3 +529,7 @@ def oct( self ):
def hex( self ):
str = "{:x}".format(int(self._uint)).zfill(((self._nbits-1)//4)+1)
return "0x"+str

def bin_vcd(self):
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The method is named bin_vcd but then we call vcd_bin in the code below?

str = "{:b}".format(int(self._uint)).zfill(self._nbits)
return str
1 change: 1 addition & 0 deletions pymtl3/datatypes/test/bits_test.py
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Expand Up @@ -760,3 +760,4 @@ def test_bin_oct_hex():
assert Bits(15,35).bin() == "0b000000000100011"
assert Bits(15,35).oct() == "0o00043"
assert Bits(15,35).hex() == "0x0023"
assert Bits(15,35).vcd_bin() == "000000000100011"
12 changes: 6 additions & 6 deletions pymtl3/passes/tracing/VcdGenerationPass.py
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Expand Up @@ -202,7 +202,7 @@ def recurse_models( m, spaces ):
for i, net in enumerate(trimmed_value_nets):
# Convert everything to Bits to get around lack of bit struct support.
# The first cycle VCD contains the default value
bin_str = net[0]._dsl.Type().to_bits().bin()
bin_str = net[0]._dsl.Type().to_bits().vcd_bin()

print( f"b{bin_str} {net_symbol_mapping[i]}", file=vcd_file )

Expand All @@ -221,7 +221,7 @@ def recurse_models( m, spaces ):
if i != vcd_clock_net_idx ]

# Flip clock for the first cycle
print( '\n#0\nb0b1 {}\n'.format( clock_symbol ), file=vcd_file, flush=True )
print( '\n#0\n1{}\n'.format( clock_symbol ), file=vcd_file, flush=True )

# Returns a dump_vcd function that is ready to be appended to _sched.
# TODO: type check?
Expand All @@ -243,21 +243,21 @@ def dump_vcd_inner( s ):
except Exception as e:
raise TypeError(f'{e}\n - {signal} becomes another type. Please check your code.')

net_bits_bin_str = net_bits_bin.bin()
net_bits_bin_str = net_bits_bin.vcd_bin()
# `last_value` is the string form of a Bits object in binary
# e.g. '0b000' == Bits3(0).bin()
# e.g. '000' == Bits3(0).vcd_bin()
# We store strings instead of values ...
if last_values[i] != net_bits_bin_str:
last_values[i] = net_bits_bin_str
print( f'b{net_bits_bin_str} {symbol}', file=vcd_file )

# Flop clock at the end of cycle
next_neg_edge = 100 * vcd_sim_ncycles + 50
print( f'\n#{next_neg_edge}\nb0b0 {clock_symbol}', file=vcd_file )
print( f'\n#{next_neg_edge}\n0{clock_symbol}', file=vcd_file )

# Flip clock of the next cycle
next_pos_edge = next_neg_edge + 50
print( f'#{next_pos_edge}\nb0b1 {clock_symbol}\n', file=vcd_file, flush=True )
print( f'#{next_pos_edge}\n1{clock_symbol}\n', file=vcd_file, flush=True )
vcd_sim_ncycles += 1

def gen_dump_vcd( s ):
Expand Down