Adding support for Zvkgs's vgmul.vs and vghsh.vs

Author: nibrunie

disasm/disasm.cc

@@ -2176,6 +2176,13 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
     DEFINE_VECTOR_VV(vghsh_vv);
   }
 
+  if (isa->extension_enabled(EXT_ZVKGS)) {
+    // Despite its suffix, the vgmul.vv instruction
+    // is really ".v", with the form "vgmul.vv vd, vs2".
+    DEFINE_VECTOR_V(vgmul_vs); 
+    DEFINE_VECTOR_VV(vghsh_vs);
+  }
+
   if (isa->extension_enabled(EXT_ZVKNED)) {
     // Despite their suffixes, the vaes*.{vv,vs} instructions
     // are really ".v", with the form "<op>.{vv,vs} vd, vs2".

disasm/isa_parser.cc

@@ -261,6 +261,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
       extension_table[EXT_ZVFBFWMA] = true;
     } else if (ext_str == "zvkg") {
       extension_table[EXT_ZVKG] = true;
+    } else if (ext_str == "zvkgs") {
+      extension_table[EXT_ZVKGS] = true;
     } else if (ext_str == "zvkn") {
       extension_table[EXT_ZVBB] = true;
       extension_table[EXT_ZVKNED] = true;

riscv/insns/vghsh_vs.h

@@ -0,0 +1,46 @@
+// vghsh.vs vd, vs2, vs1
+
+#include "zvk_ext_macros.h"
+
+require_zvkgs;
+require(P.VU.vsew == 32);
+require_egw_fits(128);
+
+VI_ZVK_VD_VS1_VS2_NOOPERANDS_PRELOOP_EGU32x4_NOVM_LOOP(
+  {},
+  // This statement will be executed before the first execution
+  // of the loop, and only if the loop is going to be entered.
+  // We cannot use a block ( { ... } ) since we want the variables declared
+  // here to be visible in the loop block.
+  // We capture the "scalar", vs2's first element, by copy, even though
+  // the "no overlap" constraint means that vs2 should remain constant
+  // during the loop.
+  EGU32x4_t H = P.VU.elt_group<EGU32x4_t>(vs2_num, 0); EGU32x4_BREV8(H);,
+  {
+    EGU32x4_t Y = P.VU.elt_group<EGU32x4_t>(vd_num, idx_eg);;   // Current partial hash
+    EGU32x4_t X = P.VU.elt_group<EGU32x4_t>(vs1_num, idx_eg);;  // Block cipher output
+
+    EGU32x4_t Z = {};
+
+    // S = brev8(Y ^ X)
+    EGU32x4_t S;
+    EGU32x4_XOR(S, Y, X);
+    EGU32x4_BREV8(S);
+
+    for (int bit = 0; bit < 128; bit++) {
+      if (EGU32x4_ISSET(S, bit)) {
+        EGU32x4_XOREQ(Z, H);
+      }
+
+      const bool reduce = EGU32x4_ISSET(H, 127);
+      EGU32x4_LSHIFT(H);  // Left shift by 1.
+      if (reduce) {
+        H[0] ^= 0x87; // Reduce using x^7 + x^2 + x^1 + 1 polynomial
+      }
+    }
+    EGU32x4_BREV8(Z);
+    // Update the destination register.
+    EGU32x4_t &vd = P.VU.elt_group<EGU32x4_t>(vd_num, idx_eg, true);
+    EGU32x4_COPY(vd, Z);
+  }
+);

riscv/insns/vgmul_vs.h

@@ -0,0 +1,41 @@
+// vgmul.vs vd, vs2
+
+#include "zvk_ext_macros.h"
+
+require_zvkgs;
+require(P.VU.vsew == 32);
+require_egw_fits(128);
+
+VI_ZVK_VD_VS2_NOOPERANDS_PRELOOP_EGU32x4_NOVM_LOOP(
+  {},
+  // This statement will be executed before the first execution
+  // of the loop, and only if the loop is going to be entered.
+  // We cannot use a block ( { ... } ) since we want the variables declared
+  // here to be visible in the loop block.
+  // We capture the "scalar", vs2's first element, by copy, even though
+  // the "no overlap" constraint means that vs2 should remain constant
+  // during the loop.
+  EGU32x4_t H = P.VU.elt_group<EGU32x4_t>(vs2_num, 0); EGU32x4_BREV8(H);
+  ,
+  {
+    EGU32x4_t Y = P.VU.elt_group<EGU32x4_t>(vd_num, idx_eg); // Multiplier
+    EGU32x4_BREV8(Y);
+    EGU32x4_t Z = {};
+
+    for (int bit = 0; bit < 128; bit++) {
+      if (EGU32x4_ISSET(Y, bit)) {
+        EGU32x4_XOREQ(Z, H);
+      }
+
+      bool reduce = EGU32x4_ISSET(H, 127);
+      EGU32x4_LSHIFT(H);  // Lef shift by 1
+      if (reduce) {
+        H[0] ^= 0x87; // Reduce using x^7 + x^2 + x^1 + 1 polynomial
+      }
+    }
+    EGU32x4_BREV8(Z);
+    // Update the destination register.
+    EGU32x4_t &vd = P.VU.elt_group<EGU32x4_t>(vd_num, idx_eg, true);
+    EGU32x4_COPY(vd, Z);
+  }
+);

riscv/riscv.mk.in

@@ -1033,6 +1033,10 @@ riscv_insn_ext_zvkg= \
 	vghsh_vv \
 	vgmul_vv \
 
+riscv_insn_ext_zvkgs= \
+	vghsh_vs \
+	vgmul_vs \
+
 riscv_insn_ext_zvkned = \
 	vaesdf_vs \
 	vaesdf_vv \
@@ -1091,6 +1095,10 @@ riscv_insn_ext_zvk = \
 	$(riscv_insn_ext_zvksed) \
 	$(riscv_insn_ext_zvksh) \
 
+riscv_insn_ext_zvka = \
+	$(riscv_insn_ext_zvbc32e) \
+	$(riscv_insn_ext_zvkgs) \
+
 riscv_insn_list = \
 	$(riscv_insn_ext_i) \
 	$(riscv_insn_ext_c) \
@@ -1117,6 +1125,7 @@ riscv_insn_list = \
 	$(riscv_insn_ext_zfh_zfa) \
 	$(riscv_insn_ext_zicond) \
 	$(riscv_insn_ext_zvk) \
+	$(riscv_insn_ext_zvka) \
 	$(riscv_insn_priv) \
 	$(riscv_insn_smrnmi) \
 	$(riscv_insn_svinval) \

riscv/zvk_ext_macros.h

@@ -957,6 +957,13 @@
     (DST)[bidx] = (SRC)[bidx]; \
   }
 
+// Copies a EGU32x4_t value from 'SRC' into 'DST'.
+#define EGU32x4_COPY(DST, SRC) \
+  for (std::size_t bidx = 0; bidx < 4; ++bidx) { \
+    (DST)[bidx] = (SRC)[bidx]; \
+  }
+
+
 // Performs  "MUT_A ^= CONST_B;", i.e., xor of the bytes
 // in A (mutated) with the bytes in B (unchanged).
 #define EGU8x16_XOREQ(MUT_A, CONST_B) \