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2 parents 0f88756 + 46fdf37 commit 79907efCopy full SHA for 79907ef
riscv/processor.cc
@@ -447,6 +447,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
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bool supv_double_trap = false;
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if (interrupt) {
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vsdeleg = (curr_virt && state.prv <= PRV_S) ? state.hideleg->read() : 0;
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+ vsdeleg >>= 1;
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hsdeleg = (state.prv <= PRV_S) ? (state.mideleg->read() | state.nonvirtual_sip->read()) : 0;
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bit &= ~((reg_t)1 << (max_xlen - 1));
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} else {
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