Reduce perf impact of Ziccid

Modifications are expected to be uncommon, so don't flush the I$
quite so often.

Author: aswaterman

riscv/execute.cc

@@ -226,7 +226,10 @@ void processor_t::step(size_t n)
   if (extension_enabled(EXT_ZICCID)) {
     // Ziccid requires stores eventually become visible to instruction fetch,
     // so periodically flush the I$
-    _mmu->flush_icache();
+    if (ziccid_flush_count-- == 0) {
+      ziccid_flush_count += ZICCID_FLUSH_PERIOD;
+      _mmu->flush_icache();
+    }
   }
 
   while (n > 0) {

riscv/processor.h

@@ -412,6 +412,9 @@ class processor_t : public abstract_device_t
   static const size_t OPCODE_CACHE_SIZE = 4095;
   opcode_cache_entry_t opcode_cache[OPCODE_CACHE_SIZE];
 
+  unsigned ziccid_flush_count = 0;
+  static const unsigned ZICCID_FLUSH_PERIOD = 10;
+
   bool is_handled_in_vs();
   void take_pending_interrupt() { take_interrupt(state.mip->read() & state.mie->read()); }
   void take_interrupt(reg_t mask); // take first enabled interrupt in mask