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riscv-software-src / riscv-isa-sim Public

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Vector crypto additional#1748

Draft

nibrunieAtSi5 wants to merge 5 commits intoriscv-software-src:masterriscv-software-src/riscv-isa-sim:masterfrom

nibrunieAtSi5:vector-crypto-additionalnibrunieAtSi5/riscv-isa-sim:vector-crypto-additionalCopy head branch name to clipboard

Conversation Commits5 (5)Checks Files changed

Draft

Vector crypto additional#1748
nibrunieAtSi5 wants to merge 5 commits intoriscv-software-src:masterfrom
nibrunieAtSi5:vector-crypto-additional

Commits

Commits on Oct 15, 2025

[Zvbc32e] enabling 32-bit vclmul/vclmulh
nibrunie
committed
[Zvbc32e] updating vclmul_vv comment
nibrunie
committed
Importing new encoding.h with additional vector crypto instructions
nibrunie
committed
Adding support for Zvkgs's vgmul.vs and vghsh.vs
nibrunie
committed
Extending Zvbc32e vclmul[h] to SEW 8 and 16
nibrunie
committed

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