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790eb91
spike: add --pc-harts option for per-hart start addresses
nabudahab Dec 30, 2025
c0ec2eb
Merge branch 'master' of github.com:nabudahab/riscv-isa-sim
nabudahab Dec 30, 2025
1aba5ea
Merge branch 'master' into master
nabudahab Jan 3, 2026
25be30b
Merge branch 'master' into master
nabudahab Jan 13, 2026
dadb0e1
Merge branch 'master' into master
nabudahab Jan 15, 2026
53ddce4
Merge branch 'master' into master
nabudahab Jan 21, 2026
5341580
Merge branch 'master' into master
nabudahab Jan 22, 2026
5e855e3
Merge branch 'master' into master
nabudahab Jan 26, 2026
b711d18
Rename '--pc-harts' option to '--pcs' in spike.cc and fix formatting
nabudahab Jan 26, 2026
ad89e09
Merge branch 'master' into master
nabudahab Jan 26, 2026
ea6a854
Update spike_main/spike.cc
nabudahab Jan 27, 2026
2c9a342
Update spike_main/spike.cc fix formatting
nabudahab Jan 27, 2026
71096c0
Fix formatting of help message for --pcs option
nabudahab Jan 27, 2026
820dc31
Merge branch 'master' into master
nabudahab Jan 28, 2026
df4d99e
adjust cfg.start_pc to handle the hart-specialized start_pc case
nabudahab Jan 29, 2026
8d76f0a
fix segfault caused by proc_reset being called before procs is fully …
nabudahab Jan 29, 2026
41fd53b
align formatting
nabudahab Jan 29, 2026
c1990c9
code cleanup
nabudahab Jan 29, 2026
b5f4731
Remove blank lines in spike.cc
nabudahab Jan 29, 2026
85dc1ec
Merge branch 'master' of https://github.com/riscv-software-src/riscv-…
nabudahab Feb 1, 2026
9cdc97f
Merge branch 'master' of github.com:nabudahab/riscv-isa-sim
nabudahab Feb 1, 2026
fab6dc3
move implementations of start_pc class functions to cfg.cc from cfg.h
nabudahab Feb 1, 2026
843a76c
Merge branch 'master' into master
nabudahab Feb 5, 2026
2fa9329
Merge branch 'master' into master
nabudahab Feb 10, 2026
24b27eb
Fix default to RSTVEC logic in sim_t::proc_reset()
nabudahab Feb 11, 2026
0fd9471
Merge branch 'master' into master
nabudahab Feb 13, 2026
dda37f0
Merge branch 'master' of github.com:riscv-software-src/riscv-isa-sim
nabudahab Feb 24, 2026
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21 changes: 21 additions & 0 deletions riscv/cfg.cc
Original file line number Diff line number Diff line change
Expand Up @@ -48,3 +48,24 @@ cfg_t::cfg_t()
trigger_count = 4;
cache_blocksz = 64;
}

void start_pc_t::set_global(reg_t pc)
{
global_pc = pc;
}

void start_pc_t::set_override(size_t hart_id, reg_t pc)
{
hart_pcs[hart_id] = pc;
}

std::optional<reg_t> start_pc_t::get(size_t hart_id) const
{
auto it = hart_pcs.find(hart_id);

if (it != hart_pcs.end()) {
return it->second;
} else {
return global_pc;
}
}
17 changes: 16 additions & 1 deletion riscv/cfg.h
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
#include <vector>
#include "decode.h"
#include <cassert>
#include <map>
class abstract_sim_if_t;

typedef enum {
Expand Down Expand Up @@ -59,6 +60,20 @@ class mem_cfg_t
reg_t size;
};

class start_pc_t
{
public:
void set_global(reg_t pc);

void set_override(size_t hart_id, reg_t pc);

std::optional<reg_t> get(size_t hart_id) const;

private:
std::optional<reg_t> global_pc;
std::map<size_t, reg_t> hart_pcs;
};

class cfg_t
{
public:
Expand All @@ -72,7 +87,7 @@ class cfg_t
reg_t pmpregions;
reg_t pmpgranularity;
std::vector<mem_cfg_t> mem_layout;
std::optional<reg_t> start_pc;
start_pc_t start_pc;
std::vector<size_t> hartids;
bool explicit_hartids;
bool real_time_clint;
Expand Down
6 changes: 5 additions & 1 deletion riscv/sim.cc
Original file line number Diff line number Diff line change
Expand Up @@ -360,7 +360,7 @@ void sim_t::set_rom()
{
const int reset_vec_size = 8;

reg_t start_pc = cfg->start_pc.value_or(get_entry_point());
reg_t start_pc = cfg->start_pc.get(0).value_or(get_entry_point());

uint32_t reset_vec[reset_vec_size] = {
0x297, // auipc t0,0x0
Expand Down Expand Up @@ -479,4 +479,8 @@ endianness_t sim_t::get_target_endianness() const
void sim_t::proc_reset(unsigned id)
{
debug_module.proc_reset(id);
if (id < procs.size()) {
procs[id]->get_state()->pc =
cfg->start_pc.get(id).value_or(get_entry_point());
}
}
21 changes: 20 additions & 1 deletion spike_main/spike.cc
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@
#include <limits>
#include <cinttypes>
#include <sstream>
#include <map>
#include "../VERSION"

static void help(int exit_code = 1)
Expand All @@ -46,6 +47,7 @@ static void help(int exit_code = 1)
fprintf(stderr, " --pmpgranularity=<n> PMP Granularity in bytes [default 4]\n");
fprintf(stderr, " --priv=<m|mu|msu> RISC-V privilege modes supported [default %s]\n", DEFAULT_PRIV);
fprintf(stderr, " --pc=<address> Override ELF entry point\n");
fprintf(stderr, " --pcs=<H:A,...> Override start PC for specific harts\n");
fprintf(stderr, " --hartids=<a,b,...> Explicitly specify hartids, default is 0,1,...\n");
fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n");
fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n");
Expand Down Expand Up @@ -380,7 +382,24 @@ int main(int argc, char** argv)
parser.option('m', 0, 1, [&](const char* s){cfg.mem_layout = parse_mem_layout(s);});
parser.option(0, "halted", 0, [&](const char UNUSED *s){halted = true;});
parser.option(0, "rbb-port", 1, [&](const char* s){use_rbb = true; rbb_port = atoul_safe(s);});
parser.option(0, "pc", 1, [&](const char* s){cfg.start_pc = strtoull(s, 0, 0);});
parser.option(0, "pc", 1, [&](const char* s){cfg.start_pc.set_global(strtoull(s, 0, 0));});

parser.option(0, "pcs", 1, [&](const char* s){
std::string arg(s);
std::stringstream ss(arg);
std::string pair;
while (std::getline(ss, pair, ',')) {
size_t delim = pair.find(':');
if (delim == std::string::npos) {
fprintf(stderr, "Error: --pcs format is hartid:addr,hartid:addr\n");
exit(1);
}
size_t hartid = std::stoul(pair.substr(0, delim));
reg_t addr = std::strtoull(pair.substr(delim+1).c_str(), NULL, 0);
cfg.start_pc.set_override(hartid, addr);
}
});

parser.option(0, "hartids", 1, [&](const char* s){
cfg.hartids = parse_hartids(s);
cfg.explicit_hartids = true;
Expand Down
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