Xqci spec: add fixes for reported issues, update spec version to 0.5.0

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml

@@ -8,7 +8,10 @@ base: 32
 length: 32
 description: |
   Condition Code Register with condition codes, plus a co-processor flags (_e.g._, to support floating point)
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 fields:
   CPFLAGS:
     location: 31-16

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml

@@ -8,7 +8,10 @@ address: 0x7f0
 length: 32
 base: 32
 priv_mode: M
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Enable bits for IRQs 0-31
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml

@@ -8,7 +8,10 @@ address: 0x7f1
 length: 32
 base: 32
 priv_mode: M
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Enable bits for IRQs 32-63
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml

@@ -8,7 +8,10 @@ address: 0x7f2
 length: 32
 base: 32
 priv_mode: M
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Enable bits for IRQs 64-95
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml

@@ -8,7 +8,10 @@ address: 0x7f3
 length: 32
 base: 32
 priv_mode: M
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Enable bits for IRQs 96-127
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml

@@ -8,7 +8,10 @@ address: 0x7f4
 length: 32
 base: 32
 priv_mode: M
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Enable bits for IRQs 128-159
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml

@@ -8,7 +8,10 @@ address: 0x7f5
 length: 32
 base: 32
 priv_mode: M
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Enable bits for IRQs 160-191
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml

@@ -8,7 +8,10 @@ address: 0x7f6
 length: 32
 base: 32
 priv_mode: M
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Enable bits for IRQs 192-223
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml

@@ -8,7 +8,10 @@ address: 0x7f7
 length: 32
 base: 32
 priv_mode: M
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Enable bits for IRQs 224-255
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml

@@ -8,7 +8,10 @@ address: 0x7f0
 length: 32
 priv_mode: M
 base: 32
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Pending bits for IRQs 0-31
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml

@@ -8,7 +8,10 @@ address: 0x7f1
 length: 32
 priv_mode: M
 base: 32
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Pending bits for IRQs 32-63
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml

@@ -8,7 +8,10 @@ address: 0x7f2
 length: 32
 priv_mode: M
 base: 32
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Pending bits for IRQs 64-95
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml

@@ -8,7 +8,10 @@ address: 0x7f3
 length: 32
 priv_mode: M
 base: 32
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Pending bits for IRQs 96-127
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml

@@ -8,7 +8,10 @@ address: 0x7f4
 length: 32
 priv_mode: M
 base: 32
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Pending bits for IRQs 128-159
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml

@@ -8,7 +8,10 @@ address: 0x7f5
 length: 32
 priv_mode: M
 base: 32
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Pending bits for IRQs 160-191
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml

@@ -8,7 +8,10 @@ address: 0x7f6
 length: 32
 priv_mode: M
 base: 32
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Pending bits for IRQs 192-223
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml

@@ -8,7 +8,10 @@ address: 0x7f7
 length: 32
 priv_mode: M
 base: 32
-definedBy: Xqci
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 description: |
   Pending bits for IRQs 224-255
 fields:

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mncause.yaml

@@ -0,0 +1,65 @@
+$schema: csr_schema.json#
+kind: csr
+name: qc_mncause
+long_name: Machine NMI Cause
+address: 0x7c2
+base: 32
+priv_mode: M
+length: MXLEN
+description: |
+  Reports the cause of the latest non-maskable interrupt.
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
+fields:
+  INT:
+    type: RW-H
+    reset_value: 0
+    location: 31
+    description: Interrupt bit copied from mcause.INT at the moment of NMI
+  NMI:
+    type: RW-H
+    reset_value: 0
+    location: 30
+    description: If 1'b1, currently processing NMI.
+  MPP:
+    type: RW-H
+    reset_value: 3
+    location: 29-28
+    description: M-mode Previous Privilege.
+  MPIE:
+    type: RW-H
+    reset_value: 0
+    location: 27
+    description: M-mode Previous Interrupt Enable.
+  MIE:
+    type: RW-H
+    reset_value: 0
+    location: 26
+    description: M-mode Interrupt Enable.
+  EXCP:
+    type: RW-H
+    reset_value: 0
+    location: 25
+    description: Exception Pending Bit.
+  RESP:
+    type: RW-H
+    reset_value: 0
+    location: 24
+    description: Resume Pending Bit.
+  MPIL:
+    type: RW-H
+    reset_value: 0
+    location: 19-16
+    description: M-mode Previous Interrupt Level.
+  MIL:
+    type: RW-H
+    reset_value: 15
+    location: 15-12
+    description: M-mode Interrupt Level.
+  NMICODE:
+    type: RW-H
+    reset_value: 0
+    location: 11-0
+    description: NMI code ID.

cfgs/qc_iu/arch_overlay/ext/Xqci.yaml

@@ -92,6 +92,48 @@ versions:
   requires:
     name: Zca
     version: ">= 1.0.0"
+- version: "0.5.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Added Xqciio sub-extension
+    - Added Xqcisim sub-extension
+    - Added Xqcisync sub-extension
+    - Fix description of qc.shladd instruction
+    - Fix description and functionality of qc.c.extu instruction
+    - Fix description and functionality of qc.wrapi instruction
+    - Fix description of qc.swmi, qc.lwmi and qc.setwmi instructions
+    - Fix description of qc.mclici* CSRs to reflect being part of Xqciint custom extension
+    - Fix description of qc.setinti and qc.clrinti instructions
+  implies:
+  - [Xqcia, "0.3.0"]
+  - [Xqciac, "0.3.0"]
+  - [Xqcibi, "0.2.0"]
+  - [Xqcibm, "0.3.0"]
+  - [Xqcicli, "0.2.0"]
+  - [Xqcicm, "0.2.0"]
+  - [Xqcics, "0.2.0"]
+  - [Xqcicsr, "0.2.0"]
+  - [Xqciint, "0.3.0"]
+  - [Xqciio, "0.1.0"]
+  - [Xqcilb, "0.2.0"]
+  - [Xqcili, "0.2.0"]
+  - [Xqcilia, "0.2.0"]
+  - [Xqcilo, "0.2.0"]
+  - [Xqcilsm, "0.3.0"]
+  - [Xqcisim, "0.1.0"]
+  - [Xqcisls, "0.2.0"]
+  - [Xqcisync, "0.1.0"]
+  requires:
+    name: Zca
+    version: ">= 1.0.0"
 description: |
   The Xqci extension includes a set of instructions that improve RISC-V code density and
   performance in microontrollers. It fills several gaps:

cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml

@@ -28,6 +28,18 @@ versions:
     email: [email protected]
   changes:
     - Add information about instruction formats of each instruction
+- version: "0.3.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix description and functionality of qc.wrapi instruction
 description: |
   The Xqcia extension includes eleven instructions to perform integer arithmetic.
 

cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml

@@ -30,6 +30,20 @@ versions:
     - Add information about instruction formats of each instruction
     - Fix description and functionality of qc.shladd instruction
   requires: { name: Zca, version: ">= 1.0.0" }
+- version: "0.3.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix description and functionality of qc.shladd instruction
+    - Renaming instructions qc.muladdi to qc.muliadd and qc.c.muladdi to qc.c.muliadd
+  requires: { name: Zca, version: ">= 1.0.0" }
 description: |
   The Xqciac extension includes three instructions to accelerate common
   address calculations.

cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml

@@ -30,6 +30,19 @@ versions:
     - Add information about instruction formats of each instruction
     - Fix description and functionality of qc.c.extu instruction
   requires: { name: Zca, version: ">= 1.0.0" }
+- version: "0.3.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix description and functionality of qc.c.extu instruction
+  requires: { name: Zca, version: ">= 1.0.0" }
 description: |
   The Xqcibm extension includes thirty eight instructions that perform bit manipulation,
   include insertion and extraction.

cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml

@@ -29,6 +29,20 @@ versions:
   changes:
     - Add information about instruction formats of each instruction
   requires: { name: Zca, version: ">= 1.0.0" }
+- version: "0.3.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix description of qc.mclici* CSRs to reflect being part of Xqciint custom extension
+    - Fix description of qc.setinti and qc.clrinti instructions
+  requires: { name: Zca, version: ">= 1.0.0" }
 description: |
   The Xqciint extension includes eleven instructions to accelerate interrupt
   servicing by performing common actions during ISR prologue/epilogue.