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rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list #146530

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Merged
merged 1 commit into from
Sep 16, 2025
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rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list #146530

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1 change: 1 addition & 0 deletions compiler/rustc_codegen_llvm/src/asm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -240,6 +240,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
}
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
constraints.extend_from_slice(&[
"~{fflags}".to_string(),
"~{vtype}".to_string(),
"~{vl}".to_string(),
"~{vxsat}".to_string(),
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2 changes: 1 addition & 1 deletion tests/codegen-llvm/asm/riscv-clobbers.rs
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Expand Up @@ -17,7 +17,7 @@ extern crate minicore;
use minicore::*;

// CHECK-LABEL: @flags_clobber
// CHECK: call void asm sideeffect "", "~{vtype},~{vl},~{vxsat},~{vxrm}"()
// CHECK: call void asm sideeffect "", "~{fflags},~{vtype},~{vl},~{vxsat},~{vxrm}"()
#[no_mangle]
pub unsafe fn flags_clobber() {
asm!("", options(nostack, nomem));
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