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rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list #146530
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rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list #146530
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"Against the reference" might be an exaggeration. Still, I think they should be added to the default clobber list. |
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I'm having trouble understanding what "Against the reference" means here. Do you mean that the reference is incorrect? Or the reference is correct but the code currently does something different? @taiki-e: I know nothing about RISC-V. You wrote |
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cc @Amanieu |
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I'll rewrite the commit message and I'll write a part of the draft v2 below (for clarity). Despite that the |
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I'm investigating the LLVM source code for interactions between subset/superset registers (e.g. About adding
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Despite that the `fflags` register (representing floating point exception flags) is stated as a flag register in the reference, it's not in the default clobber list of the RISC-V inline assembly and it would be better to fix it.
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This PR was rebased onto a different master commit. Here's a range-diff highlighting what actually changed. Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers. |
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Removed |
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Looking at the LLVM source code, relations between But it seems at least Clang does not support clobbering |
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We don't need to clobber vcsr since we already clobber vxrm and vxsat separately. There is nothing else in vcsr. |
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@bors r+ rollup |
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I'm not yet sure (e.g. what will happen if |
…ber-float-flags, r=Amanieu rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list Despite that the `fflags` register (representing floating point exception flags) is stated as a flag register [in the reference](https://doc.rust-lang.org/reference/inline-assembly.html#r-asm.rules.preserved-registers), it's not in the default clobber list of the RISC-V inline assembly and it would be better to fix it.
Rollup of 8 pull requests Successful merges: - #146402 (interpret: fix overlapping aggregate initialization) - #146530 (rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list) - #146533 (Note some previous attempts to change the Default impl for `[T; 0]`) - #146539 (fix 404 MCP link) - #146546 (Switch `std::vec::PeekMut::pop` from self to this parameter.) - #146549 (On FreeBSD, use readdir instead of readdir_r) - #146559 (Fix typo in error message) - #146563 (bootstrap.py: disable incremental build for bootstrap in CI) r? `@ghost` `@rustbot` modify labels: rollup
Rollup of 8 pull requests Successful merges: - #146402 (interpret: fix overlapping aggregate initialization) - #146530 (rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list) - #146533 (Note some previous attempts to change the Default impl for `[T; 0]`) - #146539 (fix 404 MCP link) - #146546 (Switch `std::vec::PeekMut::pop` from self to this parameter.) - #146549 (On FreeBSD, use readdir instead of readdir_r) - #146559 (Fix typo in error message) - #146563 (bootstrap.py: disable incremental build for bootstrap in CI) r? `@ghost` `@rustbot` modify labels: rollup
Rollup of 8 pull requests Successful merges: - #146402 (interpret: fix overlapping aggregate initialization) - #146530 (rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list) - #146533 (Note some previous attempts to change the Default impl for `[T; 0]`) - #146539 (fix 404 MCP link) - #146546 (Switch `std::vec::PeekMut::pop` from self to this parameter.) - #146549 (On FreeBSD, use readdir instead of readdir_r) - #146559 (Fix typo in error message) - #146563 (bootstrap.py: disable incremental build for bootstrap in CI) r? `@ghost` `@rustbot` modify labels: rollup
…ber-float-flags, r=Amanieu rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list Despite that the `fflags` register (representing floating point exception flags) is stated as a flag register [in the reference](https://doc.rust-lang.org/reference/inline-assembly.html#r-asm.rules.preserved-registers), it's not in the default clobber list of the RISC-V inline assembly and it would be better to fix it.
…ber-float-flags, r=Amanieu rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list Despite that the `fflags` register (representing floating point exception flags) is stated as a flag register [in the reference](https://doc.rust-lang.org/reference/inline-assembly.html#r-asm.rules.preserved-registers), it's not in the default clobber list of the RISC-V inline assembly and it would be better to fix it.
Rollup of 12 pull requests Successful merges: - #146338 (Extends AArch64 branch protection support to include GCS) - #146344 (tests/codegen-llvm: Make rust-abi-arch-specific-adjustment portable) - #146402 (interpret: fix overlapping aggregate initialization) - #146405 (Add relnotes for 1.90.0) - #146530 (rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list) - #146533 (Note some previous attempts to change the Default impl for `[T; 0]`) - #146539 (fix 404 MCP link) - #146546 (Switch `std::vec::PeekMut::pop` from self to this parameter.) - #146549 (On FreeBSD, use readdir instead of readdir_r) - #146559 (Fix typo in error message) - #146563 (bootstrap.py: disable incremental build for bootstrap in CI) - #146576 (opt-dist: don't set `RUST_LOG=collector=debug`) r? `@ghost` `@rustbot` modify labels: rollup
…ber-float-flags, r=Amanieu rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list Despite that the `fflags` register (representing floating point exception flags) is stated as a flag register [in the reference](https://doc.rust-lang.org/reference/inline-assembly.html#r-asm.rules.preserved-registers), it's not in the default clobber list of the RISC-V inline assembly and it would be better to fix it.
Rollup of 9 pull requests Successful merges: - #146344 (tests/codegen-llvm: Make rust-abi-arch-specific-adjustment portable) - #146530 (rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list) - #146533 (Note some previous attempts to change the Default impl for `[T; 0]`) - #146539 (fix 404 MCP link) - #146546 (Switch `std::vec::PeekMut::pop` from self to this parameter.) - #146549 (On FreeBSD, use readdir instead of readdir_r) - #146559 (Fix typo in error message) - #146563 (bootstrap.py: disable incremental build for bootstrap in CI) - #146576 (opt-dist: don't set `RUST_LOG=collector=debug`) r? `@ghost` `@rustbot` modify labels: rollup
Rollup merge of #146530 - a4lg:riscv-inline-asm-default-clobber-float-flags, r=Amanieu rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list Despite that the `fflags` register (representing floating point exception flags) is stated as a flag register [in the reference](https://doc.rust-lang.org/reference/inline-assembly.html#r-asm.rules.preserved-registers), it's not in the default clobber list of the RISC-V inline assembly and it would be better to fix it.
Despite that the
fflagsregister (representing floating point exception flags) is stated as a flag register in the reference, it's notin the default clobber list of the RISC-V inline assembly and it would be better to fix it.
Related
@rustbot label +O-riscv