drivers: spi_esp32: reapply configuration on each transfer

drivers/spi/spi_esp32_spim.c

@@ -401,14 +401,20 @@
 	spi_hal_dev_config_t *hal_dev = &data->dev_config;
 	int freq;
 
-	if (spi_context_configured(ctx, spi_cfg)) {
-		return 0;
-	}
-
-	ctx->config = spi_cfg;
-
-	if (spi_cfg->operation & SPI_HALF_DUPLEX) {
-		LOG_ERR("Half-duplex not supported");
+       /*
+        * Always reapply the hardware configuration so register state remains
+        * consistent across transactions even when the same spi_config pointer
+        * is reused.  The ESP32 HAL updates a number of user and clock
+        * registers as part of each transfer and these need to be reprogrammed
+        * before the next transaction, otherwise subsequent transfers inherit
+        * the modified state.
+        */
+       ctx->config = spi_cfg;
+
+	bool request_half_duplex = (spi_cfg->operation & SPI_HALF_DUPLEX) != 0U;
+
+	if (request_half_duplex && !cfg->half_duplex) {
+		LOG_ERR("Half-duplex requested but not enabled in devicetree");
 		return -ENOTSUP;
 	}
 
@@ -430,6 +436,9 @@
 		return ret;
 	}
 
+	hal_dev->half_duplex = cfg->half_duplex || request_half_duplex;
+	hal_dev->sio = cfg->sio && hal_dev->half_duplex;
+
 	/* input parameters to calculate timing configuration */
 	spi_hal_timing_param_t timing_param = {
 		.half_duplex = hal_dev->half_duplex,
@@ -658,6 +667,8 @@
 		.dma_enabled = DT_INST_PROP(idx, dma_enabled),	\
 		.dma_host = DT_INST_PROP(idx, dma_host),	\
 		SPI_DMA_CFG(idx),				\
+		.half_duplex = DT_INST_PROP(idx, half_duplex), \
+		.sio = DT_INST_PROP(idx, sio), \
 		.cs_setup = DT_INST_PROP_OR(idx, cs_setup_time, 0), \
 		.cs_hold = DT_INST_PROP_OR(idx, cs_hold_time, 0), \
 		.line_idle_low = DT_INST_PROP(idx, line_idle_low), \

drivers/spi/spi_esp32_spim.h

@@ -44,6 +44,8 @@ struct spi_esp32_config {
 #else
 	int dma_clk_src;
 #endif
+	bool half_duplex;
+	bool sio;
 	int cs_setup;
 	int cs_hold;
 	bool line_idle_low;

samples/boards/espressif/m5stack_cores3_spi_lcd_raw/CMakeLists.txt

@@ -0,0 +1,8 @@
+cmake_minimum_required(VERSION 3.20.0)
+
+set(DTC_OVERLAY_FILE boards/m5stack_cores3.overlay)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(m5stack_cores3_spi_lcd_raw)
+
+target_sources(app PRIVATE src/main.c)

samples/boards/espressif/m5stack_cores3_spi_lcd_raw/README.rst

@@ -0,0 +1,40 @@
+.. _m5stack_cores3_spi_lcd_raw:
+
+M5Stack CoreS3 raw SPI LCD sample
+=================================
+
+Overview
+--------
+
+This sample shows how to talk to the ILI9342C based display that is fitted to
+M5Stack CoreS3 without using Zephyr's display drivers.  It enables the
+Espressif SPI controller 3-wire mode so that 9-bit transfers (command bit plus
+8 data bits) can be issued directly.  After a minimal initialization sequence a
+simple RGB gradient is written to the screen to demonstrate how to pack the
+command/data bit into the transmit stream.
+
+Requirements
+------------
+
+* `M5Stack CoreS3 <https://docs.m5stack.com/en/core/CoreS3>`_
+
+Building and running
+--------------------
+
+Use the following command to build and flash the sample::
+
+   west build -b m5stack_cores3/esp32s3/procpu \
+     samples/boards/espressif/m5stack_cores3_spi_lcd_raw --pristine
+   west flash
+
+After programming the board and resetting it the display should shortly show a
+full-screen colour gradient and the console will print status messages similar
+to::
+
+   *** Booting Zephyr OS build v3.x.x ***
+   [00:00:00.025,000] <inf> spi_lcd_raw: Resetting LCD
+   [00:00:00.320,000] <inf> spi_lcd_raw: Drawing gradient
+   [00:00:00.750,000] <inf> spi_lcd_raw: Gradient complete
+
+The SD card slot is disabled by the sample overlay while the display is driven
+in half-duplex 3-wire mode.

samples/boards/espressif/m5stack_cores3_spi_lcd_raw/boards/m5stack_cores3.overlay

@@ -0,0 +1,17 @@
+&spi2 {
+	status = "okay";
+	half-duplex;
+	sio;
+
+        lcd_spi: display@0 {
+                compatible = "zephyr,spi-device";
+                reg = <0>;
+                spi-max-frequency = <20000000>;
+                spi-interframe-delay-ns = <0>;
+                status = "okay";
+        };
+};
+
+&sd0 {
+	status = "disabled";
+};

samples/boards/espressif/m5stack_cores3_spi_lcd_raw/prj.conf

@@ -0,0 +1,4 @@
+CONFIG_LOG=y
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_MAIN_STACK_SIZE=4096
+CONFIG_SPI=y

samples/boards/espressif/m5stack_cores3_spi_lcd_raw/sample.yaml

@@ -0,0 +1,14 @@
+sample:
+  description: Raw SPI access to the CoreS3 LCD using 3-wire mode
+  name: m5stack_cores3_spi_lcd_raw
+
+common:
+  tags:
+    - display
+    - spi
+
+tests:
+  sample.boards.espressif.m5stack_cores3_spi_lcd_raw:
+    build_only: true
+    platform_allow:
+      - m5stack_cores3/esp32s3/procpu