Fix SysCfg hardfault, Add I2C Fast Mode Plus enable method #221
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The `SysCfg` peripheral used bit banding to set the APB2 peripheral clock enable bit which fails on an assertion on a G431KBT (have not tested on other chips, but I suspect they would do the same). This takes a mutable reference to `Rcc` in `SysCfg::constrain` and uses safe accessors to enable the clock.
Updated and tested the button example which is all that uses SysCfg.
```[INFO ] Configuring PLL (stm32_foc stm32-foc/src/main.rs:132)
[INFO ] System clock frequency: 168000000 (stm32_foc stm32-foc/src/main.rs:138)
[DEBUG] Write 20007FB0 (stm32g4xx_hal stm32g4xx-hal/src/bb.rs:42)
[ERROR] panicked at /Users/fuzz/wave/stm32g4xx-hal/src/bb.rs:44:5:
assertion failed: (PERI_ADDRESS_START..=PERI_ADDRESS_END).contains(&addr) (panic_probe panic-probe-1.0.0/src/lib.rs:104)
Firmware exited unexpectedly: Multiple
Core 0
Frame 0: HardFault_ @ 0x08006394
/Users/fuzz/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-rt-0.7.5/src/lib.rs:1103:1
Frame 1: HardFault <Cause: Escalated UsageFault <Cause: Undefined instruction>> @ 0x08005ce2```
examples/button.rs
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| dp.DBGMCU.cr().modify(|_, w| { | ||
| w.dbg_sleep().set_bit(); | ||
| w.dbg_stop().set_bit(); | ||
| w.dbg_standby().set_bit() | ||
| }); |
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probe-rs should do it automatically on connect.
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@boondocklabs , if the DMA enable thing is enough, then how about we do only that? (Same for #214 i presume)
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I've removed the DBGMCU modification, and left the DMA enable in the button example. Tested on a G431KB without explicit DGBMCU modification and it does not hardfault as long as the DMA enable workaround is there.
I use DMA clock trick works on G431 and G474 The isb after wfi trick didn't work either. Lots of discussion about it on probe-rs/probe-rs#350 (comment) |
src/syscfg.rs
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| } | ||
| fn constrain(self, rcc: &mut Rcc) -> SysCfg { | ||
| // Enable SYSCFG peripheral clock in APB2ENR register | ||
| rcc.apb2enr().modify(|_, w| w.syscfgen().set_bit()); |
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I have not tinkered with the SysCfg, but is there any reason to handle this different from for example how the usarts are enabled. So something like this?
SYSCFG::enable(rcc);
SYSCFG::reset(rcc);There was a problem hiding this comment.
I'll take a look!
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Pushed a change to use Enable and Reset traits rather than direct register access
…automatically by probe-rs
… plus example using an AS5600 magnetic angle sensor
boondocklabs
changed the title
examples/i2c-fmp-as5600.rs
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| //! | ||
| //! The I2C bus is configured with Fast Mode Plus (FMP) enabled in SysCfg, and a 1MHz I2C clock rate. | ||
| //! | ||
| //! ```DEFMT_LOG=debug cargo run --release --example rand --features stm32g431,defmt -- --chip STM32G431KBTx``` |
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This is not the rand example :)
| .vos(stm32g4xx_hal::pwr::VoltageScale::Range1 { enable_boost: true }) | ||
| .freeze(); | ||
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| let pll_cfg = hal::rcc::PllConfig { |
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Do you think it would make sense and be possible to use the HSI so as not to require an external clock source?
| let mut syscfg = dp.SYSCFG.constrain(&mut rcc); | ||
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| // Enable Fast Mode Plus for I2C1 | ||
| syscfg.i2c_fmp_enable::<1>(true); |
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How does the user figure out if they should pass a 1 here or something else?
The
SysCfgperipheral used bit banding to set the APB2 peripheral clock enable bit which fails on an assertion on a G431KBT (have not tested on other chips, but I suspect they would do the same). This takes a mutable reference toRccinSysCfg::constrainand uses safe accessors to enable the clock.Updated and tested the button example which is all that uses SysCfg.