Skip to content

Update for new pac #28

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 5 commits into from
Jan 6, 2025
Merged

Update for new pac #28

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
65b58fb
Update for new pac
usbalbin Dec 18, 2024
713a31f
fmt
usbalbin Dec 18, 2024
90a989a
Dont use local pac
usbalbin Dec 18, 2024
3cf5d9b
Use staging pac
usbalbin Jan 6, 2025
ccf4e47
Fix errors due to new pac
usbalbin Jan 6, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion Cargo.toml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ log-semihost = ["log"]

[dependencies]
cortex-m = { version = "^0.7.7", features = ["critical-section-single-core"] }
stm32h5 = "0.15.1"
stm32h5 = { package = "stm32h5-staging", version = "0.17.0" }
fugit = "0.3.7"
embedded-hal = "1.0.0"
defmt = { version = "0.3.8", optional = true }
Expand Down
28 changes: 15 additions & 13 deletions src/gpio.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -318,11 +318,9 @@ where
let offset = 2 * { N };

unsafe {
(*Gpio::<P>::ptr()).ospeedr().modify(|r, w| {
w.bits(
(r.bits() & !(0b11 << offset)) | ((speed as u32) << offset),
)
});
(*Gpio::<P>::ptr())
.ospeedr()
.modify(|_r, w| w.ospeed(offset).bits(speed as u8));
}
}

Expand All @@ -340,11 +338,11 @@ where
/// Set the internal pull-up and pull-down resistor
pub fn set_internal_resistor(&mut self, resistor: Pull) {
let offset = 2 * { N };
let value = resistor as u32;
let value = resistor as u8;
unsafe {
(*Gpio::<P>::ptr()).pupdr().modify(|r, w| {
w.bits((r.bits() & !(0b11 << offset)) | (value << offset))
});
(*Gpio::<P>::ptr())
.pupdr()
.modify(|_r, w| w.pupd(offset).bits(value));
}
}

Expand Down Expand Up @@ -428,22 +426,26 @@ impl<const P: char, const N: u8, MODE> Pin<P, N, MODE> {
#[inline(always)]
fn _set_high(&mut self) {
// NOTE(unsafe) atomic write to a stateless register
unsafe { (*Gpio::<P>::ptr()).bsrr().write(|w| w.bits(1 << N)) }
unsafe {
(*Gpio::<P>::ptr()).bsrr().write(|w| w.bs(N).set_bit());
}
}
#[inline(always)]
fn _set_low(&mut self) {
// NOTE(unsafe) atomic write to a stateless register
unsafe { (*Gpio::<P>::ptr()).bsrr().write(|w| w.bits(1 << (16 + N))) }
unsafe {
(*Gpio::<P>::ptr()).bsrr().write(|w| w.br(N).set_bit());
}
}
#[inline(always)]
fn _is_set_low(&self) -> bool {
// NOTE(unsafe) atomic read with no side effects
unsafe { (*Gpio::<P>::ptr()).odr().read().bits() & (1 << N) == 0 }
unsafe { (*Gpio::<P>::ptr()).odr().read().od(N).is_low() }
}
#[inline(always)]
fn _is_low(&self) -> bool {
// NOTE(unsafe) atomic read with no side effects
unsafe { (*Gpio::<P>::ptr()).idr().read().bits() & (1 << N) == 0 }
unsafe { (*Gpio::<P>::ptr()).idr().read().id(N).is_low() }
}
}

Expand Down
2 changes: 1 addition & 1 deletion src/gpio/exti.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -142,7 +142,7 @@ where
Edge::Rising => exti.rpr1().write(|w| w.bits(mask)),
Edge::Falling => exti.fpr1().write(|w| w.bits(mask)),
_ => panic!("Must choose a rising or falling edge"),
}
};
}
}

Expand Down
8 changes: 4 additions & 4 deletions src/gpio/partially_erased.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -62,17 +62,17 @@ impl<const P: char, MODE> PartiallyErasedPin<P, Output<MODE>> {
#[inline(always)]
pub fn set_high(&mut self) {
// NOTE(unsafe) atomic write to a stateless register
unsafe { (*Gpio::<P>::ptr()).bsrr().write(|w| w.bits(1 << self.i)) }
unsafe {
(*Gpio::<P>::ptr()).bsrr().write(|w| w.bs(self.i).set_bit());
}
}

/// Drives the pin low
#[inline(always)]
pub fn set_low(&mut self) {
// NOTE(unsafe) atomic write to a stateless register
unsafe {
(*Gpio::<P>::ptr())
.bsrr()
.write(|w| w.bits(1 << (self.i + 16)))
(*Gpio::<P>::ptr()).bsrr().write(|w| w.br(self.i).set_bit());
}
}

Expand Down
14 changes: 7 additions & 7 deletions src/rcc.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -686,11 +686,11 @@ impl Rcc {
w.mco1sel()
.variant(self.config.mco1.source)
.mco1pre()
.bits(mco_1_pre)
.set(mco_1_pre)
.mco2sel()
.variant(self.config.mco2.source)
.mco2pre()
.bits(mco_2_pre)
.set(mco_2_pre)
});

// HSE
Expand Down Expand Up @@ -748,7 +748,7 @@ impl Rcc {

// Ensure core prescaler value is valid before future lower
// core voltage
while rcc.cfgr2().read().hpre().variant() != Some(hpre_bits) {}
while rcc.cfgr2().read().hpre().variant() != hpre_bits {}

// Peripheral Clock (per_ck)
rcc.ccipr5().modify(|_, w| w.ckpersel().variant(ckpersel));
Expand Down Expand Up @@ -806,10 +806,10 @@ impl Rcc {
let cfgr2 = rcc.cfgr2().read();
debug!(
"CFGR2 register: HPRE={:?} PPRE1={:?} PPRE2={:?} PPRE3={:?}",
cfgr2.hpre().variant().unwrap(),
cfgr2.ppre1().variant().unwrap(),
cfgr2.ppre2().variant().unwrap(),
cfgr2.ppre3().variant().unwrap(),
cfgr2.hpre().variant(),
cfgr2.ppre1().variant(),
cfgr2.ppre2().variant(),
cfgr2.ppre3().variant(),
);

let pll1cfgr = rcc.pll1cfgr().read();
Expand Down
12 changes: 6 additions & 6 deletions src/rcc/pll.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -224,7 +224,7 @@ macro_rules! pll_divider_setup {

// Setup divider
$rcc.[<$pllX divr>]().modify(|_, w|
w.[<$pllX $d>]().variant((pll_x_d.div - 1) as u8)
w.[<$pllX $d>]().set((pll_x_d.div - 1) as u8)
);
$rcc.[<$pllX cfgr>]().modify(|_, w| w.[<$pllX $d en>]().enabled());
Some(Hertz::from_raw($vco_ck / pll_x_d.div))
Expand Down Expand Up @@ -264,14 +264,14 @@ macro_rules! pll_setup {
let pll_x_n = pll_setup.vco_out_target / pll_setup.ref_ck;

// Write dividers
rcc.[< $pllX cfgr >]().modify(|_, w|
rcc.[< $pllX cfgr >]().modify(|_, w| unsafe {
w.[< $pllX m >]()
.variant(pll_setup.pll_m as u8)); // ref prescaler
.bits(pll_setup.pll_m as u8) }); // ref prescaler

// unsafe as not all values are permitted: see RM0492
assert!(pll_x_n >= PLL_N_MIN);
assert!(pll_x_n <= PLL_N_MAX);
rcc.[<$pllX divr>]().modify(|_, w| w.[<$pllX n>]().variant((pll_x_n - 1) as u16));
rcc.[<$pllX divr>]().modify(|_, w| unsafe { w.[<$pllX n>]().bits((pll_x_n - 1) as u16) });

let pll_x = pll_setup.pll_p.as_ref().or(pll_setup.pll_q.as_ref().or(pll_setup.pll_r.as_ref())).unwrap();

Expand All @@ -281,10 +281,10 @@ macro_rules! pll_setup {
// Calculate FRACN
let pll_x_fracn = calc_fracn(pll_setup.ref_ck as f32, pll_x_n as f32, pll_x.div as f32, pll_x.ck as f32);
//RCC_PLL1FRACR
rcc.[<$pllX fracr>]().modify(|_, w| w.[<$pllX fracn>]().variant(pll_x_fracn));
rcc.[<$pllX fracr>]().modify(|_, w| w.[<$pllX fracn>]().set(pll_x_fracn));
// Latch FRACN by resetting and setting it
rcc.[<$pllX cfgr>]().modify(|_, w| w.[< $pllX fracen>]().reset() );
rcc.[<$pllX cfgr>]().modify(|_, w| w.[< $pllX fracen>]().set() );
rcc.[<$pllX cfgr>]().modify(|_, w| w.[< $pllX fracen>]().set_() );

calc_vco_ck(pll_setup.ref_ck, pll_x_n, pll_x_fracn)
},
Expand Down
50 changes: 25 additions & 25 deletions src/rcc/rec.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -129,8 +129,8 @@ macro_rules! peripheral_reset_and_enable_control {
$(
$( #[ $pmeta:meta ] )*
$(($NoReset:ident))? $p:ident
$([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $ccip:ident $clk_doc:expr ])*
$([ group clk: $pk_g:ident $( $(($Variant_g:ident))* $ccip_g:ident $clk_doc_g:expr )* ])*
$([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $pk_alias:ident $ccip:ident $clk_doc:expr ])*
$([ group clk: $pk_g:ident $( $(($Variant_g:ident))* $pk_g_alias:ident $ccip_g:ident $clk_doc_g:expr )* ])*
$([ fixed clk: $clk_doc_f:expr ])*
),*
];)+) => {
Expand Down Expand Up @@ -177,10 +177,10 @@ macro_rules! peripheral_reset_and_enable_control {
$AXBn, $(($NoReset))* $p, [< $p:upper >], [< $p:lower >],
$( $pmeta )*
$(
[kernel $clk: $pk $(($Variant))* $ccip $clk_doc]
[kernel $clk: $pk $(($Variant))* $pk_alias $ccip $clk_doc]
)*
$(
[group clk: $pk_g [< $pk_g:lower >] $( $(($Variant_g))* $ccip_g $clk_doc_g )* ]
[group clk: $pk_g [< $pk_g:lower >] $( $(($Variant_g))* $pk_g_alias $ccip_g $clk_doc_g )* ]
)*
$(
[fixed clk: $clk_doc_f]
Expand Down Expand Up @@ -230,8 +230,8 @@ macro_rules! peripheral_reset_and_enable_control_generator {
$p_lower:ident, // comments, equivalent to with the paste macro.

$( $pmeta:meta )*
$([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $ccip:ident $clk_doc:expr ])*
$([ group clk: $pk_g:ident $pk_g_lower:ident $( $(($Variant_g:ident))* $ccip_g:ident $clk_doc_g:expr )* ])*
$([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $pk_alias:ident $ccip:ident $clk_doc:expr ])*
$([ group clk: $pk_g:ident $pk_g_lower:ident $( $(($Variant_g:ident))* $pk_g_alias:ident $ccip_g:ident $clk_doc_g:expr )* ])*
$([ fixed clk: $clk_doc_f:expr ])*
) => {
paste::item! {
Expand Down Expand Up @@ -388,7 +388,7 @@ macro_rules! peripheral_reset_and_enable_control_generator {
#[doc=$clk_doc]
/// kernel clock source selection
pub type [< $pk ClkSel >] =
rcc::[< $ccip >]::[< $pk:upper SEL >];
rcc::[< $ccip >]::[< $pk_alias SEL >];
)*
$( // Group kernel clocks
impl [< $pk_g ClkSelGetter >] for $p {}
Expand All @@ -398,7 +398,7 @@ macro_rules! peripheral_reset_and_enable_control_generator {
#[doc=$clk_doc_g]
/// kernel clock source selection.
pub type [< $pk_g ClkSel >] =
rcc::[< $ccip_g >]::[< $pk_g:upper SEL >];
rcc::[< $ccip_g >]::[< $pk_g_alias SEL >];

/// Can return
#[doc=$clk_doc_g]
Expand Down Expand Up @@ -508,8 +508,8 @@ peripheral_reset_and_enable_control! {
];
#[cfg(feature = "rm0492")]
AHB2, "" => [
Rng [kernel clk: Rng ccipr5 "RNG"],
Adc [group clk: AdcDac(Variant) ccipr5 "ADC/DAC"],
Rng [kernel clk: Rng RNG ccipr5 "RNG"],
Adc [group clk: AdcDac(Variant) ADCDAC ccipr5 "ADC/DAC"],
Dac12 [group clk: AdcDac]
];

Expand All @@ -522,16 +522,16 @@ peripheral_reset_and_enable_control! {
];
#[cfg(feature = "rm0492")]
APB1L, "" => [
I3c1 [kernel clk: I3c1(Variant) ccipr4 "I3C1"],
I3c1 [kernel clk: I3c1(Variant) I3C ccipr4 "I3C1"],

I2c1 [kernel clk: I2c1 ccipr4 "I2C1"],
I2c2 [kernel clk: I2c2 ccipr4 "I2C2"],
I2c1 [kernel clk: I2c1 I2C ccipr4 "I2C1"],
I2c2 [kernel clk: I2c2 I2C ccipr4 "I2C2"],

Usart2 [kernel clk: Usart2(Variant) ccipr1 "USART2"],
Usart3 [kernel clk: Usart3(Variant) ccipr1 "USART3"],
Usart2 [kernel clk: Usart2(Variant) USART ccipr1 "USART2"],
Usart3 [kernel clk: Usart3(Variant) USART ccipr1 "USART3"],

Spi2 [kernel clk: Spi2(Variant) ccipr3 "SPI2"],
Spi3 [kernel clk: Spi3(Variant) ccipr3 "SPI3"],
Spi2 [kernel clk: Spi2(Variant) SPI123 ccipr3 "SPI2"],
Spi3 [kernel clk: Spi3(Variant) SPI123 ccipr3 "SPI3"],
Opamp,
Comp
];
Expand All @@ -542,8 +542,8 @@ peripheral_reset_and_enable_control! {
];
#[cfg(feature = "rm0492")]
APB1H, "" => [
Lptim2 [kernel clk: Lptim2(Variant) ccipr2 "LPTIM2"],
Fdcan [kernel clk: Fdcan(Variant) ccipr5 "FDCAN"]
Lptim2 [kernel clk: Lptim2(Variant) LPTIM ccipr2 "LPTIM2"],
Fdcan [kernel clk: Fdcan(Variant) FDCAN ccipr5 "FDCAN"]
];

#[cfg(all())]
Expand All @@ -552,9 +552,9 @@ peripheral_reset_and_enable_control! {
];
#[cfg(feature = "rm0492")]
APB2, "" => [
Usb [kernel clk: Usb ccipr4 "USB"],
Usart1 [kernel clk: Usart1(Variant) ccipr1 "USART1"],
Spi1 [kernel clk: Spi1(Variant) ccipr3 "SPI1"]
Usb [kernel clk: Usb USB ccipr4 "USB"],
Usart1 [kernel clk: Usart1(Variant) USART ccipr1 "USART1"],
Spi1 [kernel clk: Spi1(Variant) SPI123 ccipr3 "SPI1"]
];

#[cfg(all())]
Expand All @@ -564,9 +564,9 @@ peripheral_reset_and_enable_control! {
];
#[cfg(feature = "rm0492")]
APB3, "" => [
I3c2 [kernel clk: I3c2(Variant) ccipr4 "I3C2"],
LpTim1 [kernel clk: LpTim1(Variant) ccipr2 "LPTIM1"],
LpUart1 [kernel clk: LpUart1(Variant) ccipr3 "LPUART1"]
I3c2 [kernel clk: I3c2(Variant) I3C ccipr4 "I3C2"],
LpTim1 [kernel clk: LpTim1(Variant) LPTIM ccipr2 "LPTIM1"],
LpUart1 [kernel clk: LpUart1(Variant) USART ccipr3 "LPUART1"]
];

}
Loading