Design of DP scheduling with deadline calculations #515
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architectures/firmware/sof-zephyr/mpp_layer/images/dp_scheduling/example3_5.pu
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this commit contains a detailed description of DP scheduling and DP deadline calculations Signed-off-by: Marcin Szkudlinski <[email protected]>
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Pull Request Overview
This PR adds comprehensive documentation for DP (Data Processing) scheduling with deadline calculations in the SOF firmware architecture. It introduces a detailed design document that explains the EDF (Earliest Deadline First) scheduling algorithm used for data processing modules running in separate threads with lower priority than LL (Low Latency) threads.
Key changes:
- Addition of DP scheduling documentation with mathematical formulations for deadline calculations
- Comprehensive examples demonstrating different scheduling scenarios including startup cases
- Multiple PlantUML diagrams illustrating pipeline states and data flow
Reviewed Changes
Copilot reviewed 30 out of 30 changed files in this pull request and generated 5 comments.
| File | Description |
|---|---|
| architectures/firmware/sof-zephyr/mpp_layer/index.rst | Adds reference to new dp_scheduling documentation |
| architectures/firmware/sof-zephyr/mpp_layer/dp_scheduling.rst | Main documentation file with detailed DP scheduling design and examples |
| architectures/firmware/sof-zephyr/mpp_layer/images/dp_scheduling/*.pu | 29 PlantUML diagram files showing various pipeline states and scheduling scenarios |
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| - data reciever's consumption rate and period | ||
| - data source production rate and period | ||
| - data reciever's module's LST - latest start time |
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The word 'reciever' should be spelled 'receiver' (appears twice in lines 40 and 42).
| - data reciever's consumption rate and period | |
| - data source production rate and period | |
| - data reciever's module's LST - latest start time | |
| - data receiver's consumption rate and period | |
| - data source production rate and period | |
| - data receiver's module's LST - latest start time |
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| *Example:* if a data rate is 48samples/msec and OBS = 480samples, the "worst case" period should be calculated 10ms | ||
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| *NOTE:* in case of sampling freq like 44.1 a round up should taken - if ration is 44.1 samples per mlisecond, 45 samples should be used for calculations |
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Multiple spelling errors: 'ration' should be 'ratio' and 'mlisecond' should be 'millisecond'. Also 'should taken' should be 'should be taken'.
| *NOTE:* in case of sampling freq like 44.1 a round up should taken - if ration is 44.1 samples per mlisecond, 45 samples should be used for calculations | |
| *NOTE:* in case of sampling freq like 44.1 a round up should be taken - if ratio is 44.1 samples per millisecond, 45 samples should be used for calculations |
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| **def: DP module's latest start time (LST)** | ||
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| LST is the latest time when **a module** must start processing a portion of data in order to meet its deadline. It can be calculated as: | ||
| ``deadline - LPT`` When a module is in the middle of processing, its LST may be negative. In that case 0 should be taken to all futhure calculations. |
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The word 'futhure' should be spelled 'future'.
| ``deadline - LPT`` When a module is in the middle of processing, its LST may be negative. In that case 0 should be taken to all futhure calculations. | |
| ``deadline - LPT`` When a module is in the middle of processing, its LST may be negative. In that case 0 should be taken to all future calculations. |
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| End of stream | ||
| ============= | ||
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| When a SP module is in the middle of processing when a pipeline is stopping, it should finish processing its current chunk of data. Unformtunately there's no way to interrupt ongoing processing without risk of memory leaks etc. Therefore IPC stopping a pipeline should wait till all DP modules finish processing. |
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The word 'Unformtunately' should be spelled 'Unfortunately'. Also 'SP module' appears to be inconsistent with 'DP module' used elsewhere in the document.
| When a SP module is in the middle of processing when a pipeline is stopping, it should finish processing its current chunk of data. Unformtunately there's no way to interrupt ongoing processing without risk of memory leaks etc. Therefore IPC stopping a pipeline should wait till all DP modules finish processing. | |
| When a DP module is in the middle of processing when a pipeline is stopping, it should finish processing its current chunk of data. Unfortunately there's no way to interrupt ongoing processing without risk of memory leaks etc. Therefore IPC stopping a pipeline should wait till all DP modules finish processing. |
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| - dedline of DP2 can't be calculated | ||
| - dedline of DP1 can't be calculated |
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The word 'dedline' should be spelled 'deadline' (appears twice).
| - dedline of DP2 can't be calculated | |
| - dedline of DP1 can't be calculated | |
| - deadline of DP2 can't be calculated | |
| - deadline of DP1 can't be calculated |
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this commit contains a detailed description of DP
scheduling and DP deadline calculations
readable version:
https://marcinszkudlinski.github.io/sof-docs/PAGES/architectures/firmware/sof-zephyr/mpp_layer/dp_scheduling.html