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axi-lite
Here are 32 public repositories matching this topic...
Designing means to communicate as an SPI master, being a part of AXI interface
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Sep 14, 2023 - Verilog
This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
protocol verification eda rtl verilog systemverilog alu vlsi modelsim uvm verilog-hdl axi apb ahb verilog-project vlsi-design design-verification vlsi-project axi-lite system-verilog-testbench
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Sep 13, 2025 - SystemVerilog
Registers bank with Axi-Lite interface
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Oct 22, 2022 - VHDL
🏄 Custom IP for vector operations
zynq vector vhdl vivado hardware-designs hdl custom-ip fpga-accelerator axi vitis axi-lite vector-operation vector-ops vector-operations
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Aug 31, 2024 - VHDL
FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
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Feb 20, 2023 - C
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls axi-memory-mapped
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Nov 21, 2023 - TeX
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado microblaze axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls
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Dec 3, 2023 - C
an RTL circuit that sorts the integer values in a momory unit connected with (almost) AXI-Lite
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Jul 19, 2023 - Verilog
Deterministic RTL RMS / Peak envelope detector for FPGA audio pipelines. AXI-Stream + AXI-Lite, fixed-point, cycle-accurate, real-time safe.
fpga verilog xilinx fixed-point rms audio-dsp peak-detection axi-stream axi-lite envelope-detection kria-kv260
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Feb 7, 2026 - SystemVerilog
A first-order IIR filter for 16-bit PCM stereo data implemented on an FPGA with fixed-point representation.
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Feb 7, 2026 - SystemVerilog
A deterministic, fixed-latency tanh non-linear distortion DSP block implemented in Verilog and integrated with AXI-Stream, published as a reference RTL design.
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Jan 31, 2026 - Verilog
SystemVerilog testbench with assertions and coverage for verifying AXI4-Lite protocol compliance. Simulated using Vivado XSIM CLI with WSL2.
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Jun 25, 2025 - SystemVerilog
A FIR filter for 16-bit stereo PCM audio DSP implemented on an FPGA with fixed-point representation.
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Feb 7, 2026 - SystemVerilog
UVM Verification of AXI-Lite Sram Controller
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Feb 15, 2026 - SystemVerilog
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