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Merge pull request #552 from pigmoral/eg4d20
Fix the failure of old Anlogic Cable and add support for Anlogic EG4D20EG176
2 parents e18c139 + 5fefbb3 commit f084549

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-4
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doc/FPGAs.yml

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Anlogic:
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- Description: EG4
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Model: S20
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URL: http://www.anlogic.com/prod_view.aspx?TypeId=10&Id=168&FId=t3:10:3
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Model:
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- EG4D20
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- EG4S20
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URL: https://www.anlogic.com/en/product/fpga/saleagle/eg4
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Memory: OK
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Flash: AS
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- Description: SALELF 2
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Model: EF2M45
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URL: http://www.anlogic.com/prod_view.aspx?TypeId=12&Id=170&FId=t3:12:3
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URL: https://www.anlogic.com/en/product/fpga/salelf/salelf2
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Memory: OK
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Flash: OK
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doc/boards.yml

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Memory: OK
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Flash: OK
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- ID: mlk-s200-eg4d20
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Description: MILIANKE S200 EG4D20 Development Board
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URL: https://www.milianke.com/product-item-108.html
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FPGA: eagle s20 EG4D20EG176
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Memory: OK
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Flash: OK
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- ID: mini_itx
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Description: Avnet Mini-ITX Base Kit
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URL: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/mini-itx/

src/anlogicCable.cpp

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using namespace std;
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#define ANLOGICCABLE_VIDv1 0x336C
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#define ANLOGICCABLE_VIDv1 0x0547
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#define ANLOGICCABLE_VIDv2 0x336C
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#define ANLOGICCABLE_PID 0x1002
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src/board.hpp

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@@ -193,6 +193,7 @@ static std::map <std::string, target_board_t> board_list = {
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JTAG_BOARD("machXO2EVN", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("machXO3SK", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("machXO3EVN", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("mlk-s200-eg4d20", "", "anlogicCable", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("mimas_a7", "xc7a50tfgg484", "numato", 0, 0, CABLE_MHZ(30)),
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JTAG_BOARD("neso_a7", "xc7a100tcsg324", "numato-neso", 0, 0, CABLE_MHZ(30)),
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JTAG_BOARD("minispartan6", "", "ft2232", 0, 0, CABLE_DEFAULT),

src/part.hpp

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@@ -24,6 +24,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
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/**************************************************************************/
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/* Anlogic Eagle */
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{0x04014c35, {"anlogic", "eagle d20", "EG4D20EG176", 8}},
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{0x0a014c35, {"anlogic", "eagle s20", "EG4S20BG256", 8}},
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/* Anlogic Elf2 */

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