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Fix the failure of old Anlogic Cable and add support for Anlogic EG4D20EG176 #552

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Merged
trabucayre merged 2 commits into from
May 23, 2025
Merged

Fix the failure of old Anlogic Cable and add support for Anlogic EG4D20EG176 #552

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951db00
anlogicCable: Fix wrong ANLOGICCABLE_VIDv1
pigmoral May 22, 2025
5fefbb3
Add support for MILIANKE-S200-EG4D20 and update document
pigmoral May 22, 2025
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8 changes: 5 additions & 3 deletions doc/FPGAs.yml
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Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
Anlogic:

- Description: EG4
Model: S20
URL: http://www.anlogic.com/prod_view.aspx?TypeId=10&Id=168&FId=t3:10:3
Model:
- EG4D20
- EG4S20
URL: https://www.anlogic.com/en/product/fpga/saleagle/eg4
Memory: OK
Flash: AS

- Description: SALELF 2
Model: EF2M45
URL: http://www.anlogic.com/prod_view.aspx?TypeId=12&Id=170&FId=t3:12:3
URL: https://www.anlogic.com/en/product/fpga/salelf/salelf2
Memory: OK
Flash: OK

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7 changes: 7 additions & 0 deletions doc/boards.yml
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Expand Up @@ -552,6 +552,13 @@
Memory: OK
Flash: OK

- ID: mlk-s200-eg4d20
Description: MILIANKE S200 EG4D20 Development Board
URL: https://www.milianke.com/product-item-108.html
FPGA: eagle s20 EG4D20EG176
Memory: OK
Flash: OK

- ID: mini_itx
Description: Avnet Mini-ITX Base Kit
URL: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/mini-itx/
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2 changes: 1 addition & 1 deletion src/anlogicCable.cpp
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Expand Up @@ -17,7 +17,7 @@

using namespace std;

#define ANLOGICCABLE_VIDv1 0x336C
#define ANLOGICCABLE_VIDv1 0x0547
#define ANLOGICCABLE_VIDv2 0x336C
#define ANLOGICCABLE_PID 0x1002

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1 change: 1 addition & 0 deletions src/board.hpp
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Expand Up @@ -193,6 +193,7 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("machXO2EVN", "", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("machXO3SK", "", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("machXO3EVN", "", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("mlk-s200-eg4d20", "", "anlogicCable", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("mimas_a7", "xc7a50tfgg484", "numato", 0, 0, CABLE_MHZ(30)),
JTAG_BOARD("neso_a7", "xc7a100tcsg324", "numato-neso", 0, 0, CABLE_MHZ(30)),
JTAG_BOARD("minispartan6", "", "ft2232", 0, 0, CABLE_DEFAULT),
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1 change: 1 addition & 0 deletions src/part.hpp
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Expand Up @@ -24,6 +24,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
/**************************************************************************/

/* Anlogic Eagle */
{0x04014c35, {"anlogic", "eagle d20", "EG4D20EG176", 8}},
{0x0a014c35, {"anlogic", "eagle s20", "EG4S20BG256", 8}},

/* Anlogic Elf2 */
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