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@pigmoral pigmoral commented May 22, 2025

  1. Fix ANLOGICCABLE_VIDv1 to correct old value.
  2. Add support for Anlogic EG4D20EG176 FPGA.
  3. Add support for MLK-S200-EG4D20 board.
  4. Update related document and outdated URL.
-> % ./openFPGALoader -b mlk-s200-eg4d20 --detect
empty
Jtag frequency : requested 6000000Hz -> real 6000000Hz
index 0:
        idcode 0x4014c35
        manufacturer anlogic
        family eagle d20
        model  EG4D20EG176
        irlength 8

-> % ./openFPGALoader -b mlk-s200-eg4d20 mlk_s200_eg4d20.bit
empty
Jtag frequency : requested 6000000Hz -> real 6000000Hz
Parse file header end
DONE
Loading: [===================================================] 100.00%
Done

-> % ./openFPGALoader -b mlk-s200-eg4d20 -f mlk_s200_eg4d20.bit
empty
write to flash
Jtag frequency : requested 6000000Hz -> real 6000000Hz
Parse file header end
DONE
JEDEC ID: 0xef4015
Detected: Winbond W25Q16 32 sectors size: 16Mb
00000000 00000000 00000000 00
start addr: 00000000, end_addr: 000b0000
Erasing: [==================================================] 100.00%
Done
Writing: [===================================================] 100.00%
Done

pigmoral added 2 commits May 22, 2025 10:37
ANLOGICCABLE_VIDv1 should keep the old ANLOGICCABLE_VID to compatible
with the original device.

Fixes: 4b008a0 ("anlogicCable: refresh with new VID")
Signed-off-by: Junhui Liu <[email protected]>
Add board definition and FPGA part ID for the MILIANKE S200 EG4D20
development board. Also update related documentation and outdated URL.

Tested ok by loading bitstream to SRAM and FLASH.

Signed-off-by: Junhui Liu <[email protected]>
@trabucayre trabucayre merged commit f084549 into trabucayre:master May 23, 2025
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@trabucayre
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Applied. Thanks @pigmoral !
And also thanks for the fix!

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2 participants