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Add PSRAM half Sleep and DCache support for Siwx91x #155

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Add PSRAM half Sleep and DCache support for Siwx91x #155

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a759e17
scripts: import_wiseconnect.py update
fimohame Nov 26, 2025
a053bc7
wiseconnect: D_Cache SDK files
fimohame Nov 26, 2025
a8a5464
wiseconnect: Patch for rsi_deepsleep_soc.c
fimohame Nov 26, 2025
97f48c6
wiseconnect: Patch for sli_si91x_clock_manager.c
fimohame Nov 26, 2025
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2 changes: 2 additions & 0 deletions wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c
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Expand Up @@ -78,6 +78,8 @@ extern void set_scdc(uint32_t Deepsleep);
#include "sl_si91x_psram_aps6404l_sqh_config.h"
#elif defined(SLI_SI91X_MCU_PSRAM_APS6404L_SQRH)
#include "sl_si91x_psram_aps6404l_sqrh_config.h"
#elif __ZEPHYR__
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@Martinhoff-maker Martinhoff-maker Dec 2, 2025 •
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I understand this patch but is there any actions to take in Wiseconnect in order to avoid that stuff in the next release of Wiseconnect ? Remenber that @jerome-pouiller is trying to reduce the number of patch in wiseconnect so each time we introduce a new one, we should think to remove it in the next release.

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@fimohame fimohame Dec 2, 2025

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let me check through if we can do any in here

#include "sl_si91x_psram.h"
#else
#error "No valid PSRAM configuration defined"
#endif
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