silabs: siwx91x: Fix to enable PSRAM half-sleep support to reduce sleep current #100078
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@fimohame please use prefixes in PR subjects that are meaningful to everyone working with Zephyr. I fixed it now. |
| zephyr_compile_definitions( | ||
| SLI_SI91X_MCU_PSRAM_PRESENT | ||
| SLI_SI91X_MCU_ENABLE_PSRAM_FEATURE | ||
| SL_SI91X_REQUIRES_INTF_PLL |
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This defines seems to have other impact than just QSPI. It is used in the 91x clock manager.
Seems to also have impact on pm with ps state changes :
#ifdef SL_SI91X_REQUIRES_INTF_PLL
// Set INTF PLL based on current state and mode
intf_pll_freq = power_mode ? PS4_PERFORMANCE_MODE_INTF_FREQ : PS4_POWERSAVE_MODE_FREQ;
sli_status = sl_si91x_clock_manager_set_pll_freq(INTF_PLL, intf_pll_freq, PLL_REF_CLK_VAL_XTAL);
if (sli_status != SL_STATUS_OK) {
break;
}
if (intf_pll_freq == PS4_PERFORMANCE_MODE_INTF_FREQ) {
qspi_clk_source = QSPI_INTFPLLCLK;
} else {
qspi_clk_source = QSPI_ULPREFCLK;
}
#endif /* SL_SI91X_REQUIRES_INTF_PLL */
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I have to admit SL_SI91X_REQUIRES_INTF_PLL collides with the Zephyr architecture. If I have the correct full picture, two clocks should be associated to the memc device (PLL and ULPREF). On qspi TURN_OFF/TURN_ON, the drive should call the clock_control_off()/clock_control_on() on the relevant clocks.
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With the correct support of ps_ram for dk2605a, you can also add the tag memc to the board .yaml
This commit updates the hal_silabs revision Signed-off-by: S Mohamed Fiaz <[email protected]>
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I've addressed most of the comments, but wrt to clock manager changes we might need to discuss on. Until then converting this PR to draft |
This patch adds the missing 'half-sleep-supported' and 'external-ldo' properties to the silabs,siwx91x-qspi-memory binding for accurate configuration of PSRAM features via DeviceTree. Signed-off-by: S Mohamed Fiaz <[email protected]>
…ties This commit fixes the device tree configuration by adding 'external-ldo' and 'half-sleep-supported' properties for the PSRAM device, enabling correct low-power and power source support on siwx917_dk2605a and siwx917_rb4342a boards. Signed-off-by: S Mohamed Fiaz <[email protected]>
This update fixes build system integration for PSRAM features by adding rsi_d_cache.c to the sources and required compile definitions, ensuring full support for half-sleep and LDO functionality. Signed-off-by: S Mohamed Fiaz <[email protected]>
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Previously, the PSRAM boards exhibited high sleep current due to lack of half-sleep support. This PR implements half-sleep mode for PSRAM, reducing power consumption during device sleep.
Changes include:
With these fixes, PSRAM now enters half-sleep mode correctly, resulting in lower sleep current on siwx91x-PSRAM based boards which supports half sleep mode.
Signed-off-by: S Mohamed Fiaz [email protected]