silabs: siwx91x: Fix to enable PSRAM half-sleep support to reduce sleep current

[fimohame]

Previously, the PSRAM boards exhibited high sleep current due to lack of half-sleep support. This PR implements half-sleep mode for PSRAM, reducing power consumption during device sleep.

Changes include:

• DeviceTree and bindings updated to support 'half-sleep-supported' and 'ldo' for PSRAM
• Build system updates for necessary sources and driver flags

With these fixes, PSRAM now enters half-sleep mode correctly, resulting in lower sleep current on siwx91x-PSRAM based boards which supports half sleep mode.

Signed-off-by: S Mohamed Fiaz Fiaz.Mohamed@silabs.com

[github-actions]

The following west manifest projects have changed revision in this Pull Request:

Name	Old Revision	New Revision	Diff
hal_silabs	zephyrproject-rtos/hal_silabs@091a5bb (main)	zephyrproject-rtos/hal_silabs#155	zephyrproject-rtos/hal_silabs#155/files

⛔ DNM label due to: 1 project with PR revision

Note: This message is automatically posted and updated by the Manifest GitHub Action.

[jhedberg]

@fimohame please use prefixes in PR subjects that are meaningful to everyone working with Zephyr. I fixed it now.

[Martinhoff-maker]

This defines seems to have other impact than just QSPI. It is used in the 91x clock manager.
Seems to also have impact on pm with ps state changes :

#ifdef SL_SI91X_REQUIRES_INTF_PLL
      // Set INTF PLL based on current state and mode
      intf_pll_freq = power_mode ? PS4_PERFORMANCE_MODE_INTF_FREQ : PS4_POWERSAVE_MODE_FREQ;

      sli_status = sl_si91x_clock_manager_set_pll_freq(INTF_PLL, intf_pll_freq, PLL_REF_CLK_VAL_XTAL);
      if (sli_status != SL_STATUS_OK) {
        break;
      }
      if (intf_pll_freq == PS4_PERFORMANCE_MODE_INTF_FREQ) {
        qspi_clk_source = QSPI_INTFPLLCLK;
      } else {
        qspi_clk_source = QSPI_ULPREFCLK;
      }
#endif /* SL_SI91X_REQUIRES_INTF_PLL */

[jerome-pouiller]

I have to admit SL_SI91X_REQUIRES_INTF_PLL collides with the Zephyr architecture. If I have the correct full picture, two clocks should be associated to the memc device (PLL and ULPREF). On qspi TURN_OFF/TURN_ON, the drive should call the clock_control_off()/clock_control_on() on the relevant clocks.

[Martinhoff-maker]

With the correct support of ps_ram for dk2605a, you can also add the tag memc to the board .yaml

[fimohame]

I've addressed most of the comments, but wrt to clock manager changes we might need to discuss on.

Until then converting this PR to draft

[sonarqubecloud]

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

[github-actions]

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