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Feb 15, 2021
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x86: add kconfigs and compiler flags for MMX and SSE* #31198

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59c47e0
x86: correct compiler flags for SSE
dcpleung Jan 7, 2021
e065e6f
tests: fpu_sharing: test both FPU and SSE on x86
dcpleung Jan 7, 2021
7b9cc23
tests: benchmarks/app_kernel: enable for floating point
dcpleung Jan 7, 2021
fc19aa2
x86: rename CONFIG_SSE* to CONFIG_X86_SSE*
dcpleung Jan 7, 2021
d6faf57
x86: add kconfigs and compiler flags for MMX and SSE*
dcpleung Jan 8, 2021
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120 changes: 120 additions & 0 deletions arch/x86/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,10 @@ config CPU_ATOM
select CPU_HAS_FPU
select ARCH_HAS_STACK_PROTECTION if X86_MMU
select ARCH_HAS_USERSPACE if X86_MMU
select X86_CPU_HAS_MMX
select X86_CPU_HAS_SSE
select X86_CPU_HAS_SSE2
select X86_CPU_HAS_SSE3
help
This option signifies the use of a CPU from the Atom family.

Expand All @@ -33,6 +37,14 @@ config CPU_APOLLO_LAKE
select CPU_HAS_FPU
select ARCH_HAS_STACK_PROTECTION if X86_MMU
select ARCH_HAS_USERSPACE if X86_MMU
select X86_MMU
select X86_CPU_HAS_MMX
select X86_CPU_HAS_SSE
select X86_CPU_HAS_SSE2
select X86_CPU_HAS_SSE3
select X86_CPU_HAS_SSSE3
select X86_CPU_HAS_SSE41
select X86_CPU_HAS_SSE42
help
This option signifies the use of a CPU from the Apollo Lake family.

Expand All @@ -47,6 +59,114 @@ config X86_64
select USE_SWITCH_SUPPORTED
select SCHED_IPI_SUPPORTED
select X86_MMU
select X86_CPU_HAS_MMX
select X86_CPU_HAS_SSE
select X86_CPU_HAS_SSE2
select X86_MMX
select X86_SSE
select X86_SSE2

menu "x86 Features"

config X86_CPU_HAS_MMX
bool

config X86_CPU_HAS_SSE
bool

config X86_CPU_HAS_SSE2
bool

config X86_CPU_HAS_SSE3
bool

config X86_CPU_HAS_SSSE3
bool

config X86_CPU_HAS_SSE41
bool

config X86_CPU_HAS_SSE42
bool

config X86_CPU_HAS_SSE4A
bool

if FPU || X86_64

config X86_MMX
bool "Enable MMX Support"
depends on X86_CPU_HAS_MMX
help
This option enables MMX support, and the use of MMX registers
by threads.

config X86_SSE
bool "Enable SSE Support"
depends on X86_CPU_HAS_SSE
help
This option enables SSE support, and the use of SSE registers
by threads.

config X86_SSE2
bool "Enable SSE2 Support"
depends on X86_CPU_HAS_SSE2
select X86_SSE
help
This option enables SSE2 support.

config X86_SSE3
bool "Enable SSE3 Support"
depends on X86_CPU_HAS_SSE3
select X86_SSE
help
This option enables SSE3 support.

config X86_SSSE3
bool "Enable SSSE3 (Supplemental SSE3) Support"
depends on X86_CPU_HAS_SSSE3
select X86_SSE
help
This option enables Supplemental SSE3 support.

config X86_SSE41
bool "Enable SSE4.1 Support"
depends on X86_CPU_HAS_SSE41
select X86_SSE
help
This option enables SSE4.1 support.

config X86_SSE42
bool "Enable SSE4.2 Support"
depends on X86_CPU_HAS_SSE42
select X86_SSE
help
This option enables SSE4.2 support.

config X86_SSE4A
bool "Enable SSE4A Support"
depends on X86_CPU_HAS_SSE4A
select X86_SSE
help
This option enables SSE4A support.

config X86_SSE_FP_MATH
bool "Compiler-generated SSEx instructions for floating point math"
depends on X86_SSE
help
This option allows the compiler to generate SSEx instructions for
performing floating point math. This can greatly improve performance
when exactly the same operations are to be performed on multiple
data objects; however, it can also significantly reduce performance
when preemptive task switches occur because of the larger register
set that must be saved and restored.

Disabling this option means that the compiler utilizes only the
x87 instruction set for floating point operations.

endif # FPU || X86_64

endmenu

config X86_KERNEL_OFFSET
int "Kernel offset from beginning of RAM"
Expand Down
16 changes: 5 additions & 11 deletions arch/x86/core/Kconfig.ia32
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Original file line number Diff line number Diff line change
Expand Up @@ -92,22 +92,16 @@ if CPU_HAS_FPU
config SSE
bool "SSE registers"
depends on FPU
select X86_SSE
help
This option enables the use of SSE registers by threads.
This option is deprecated. Please use CONFIG_X86_SSE instead.

config SSE_FP_MATH
bool "Compiler-generated SSEx instructions"
depends on SSE
depends on X86_SSE
select X86_SSE_FP_MATH
help
This option allows the compiler to generate SSEx instructions for
performing floating point math. This can greatly improve performance
when exactly the same operations are to be performed on multiple
data objects; however, it can also significantly reduce performance
when preemptive task switches occur because of the larger register
set that must be saved and restored.

Disabling this option means that the compiler utilizes only the
x87 instruction set for floating point operations.
This option is deprecated. Please use CONFIG_X86_SSE_FP_MATH instead.

config EAGER_FPU_SHARING
bool
Expand Down
20 changes: 10 additions & 10 deletions arch/x86/core/ia32/crt0.S
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Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@
#endif


#if defined(CONFIG_SSE)
#if defined(CONFIG_X86_SSE)
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@andrewboie andrewboie Jan 8, 2021 •
edited
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Is CONFIG_X86_SSE supposed to be a superset of all the configs like CONFIG_X86_SSE4A, for example?

Most of the asm code related to SSE applies to all SSE variants and also MMX since they are all using the same set of XMM registers

I don't think this will work if someone just selects CONFIG_X86_SSE4 for example

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Fixed to do select X86_SSE so CONFIG_X86_SSE is enabled when any SSE kconfig is enabled.

MMX registers overlay with FPU registers so only needs CONFIG_FPU.

GDATA(_sse_mxcsr_default_value)
#endif

Expand Down Expand Up @@ -101,7 +101,7 @@ __csSet:

fninit /* set x87 FPU to its default state */

#if defined(CONFIG_SSE)
#if defined(CONFIG_X86_SSE)
/*
* Permit use of SSE instructions
*
Expand All @@ -116,7 +116,7 @@ __csSet:

ldmxcsr _sse_mxcsr_default_value /* initialize SSE control/status reg */

#endif /* CONFIG_SSE */
#endif /* CONFIG_X86_SSE */

#endif /* !CONFIG_FPU */

Expand Down Expand Up @@ -236,7 +236,7 @@ __csSet:

_x86_bss_zero:
/* ECX = size, EDI = starting address */
#ifdef CONFIG_SSE
#ifdef CONFIG_X86_SSE
/* use XMM register to clear 16 bytes at a time */
pxor %xmm0, %xmm0 /* zero out xmm0 register */

Expand All @@ -258,7 +258,7 @@ bssWords:
rep
stosl /* zero memory per 4 bytes */

#else /* !CONFIG_SSE */
#else /* !CONFIG_X86_SSE */

/* clear out BSS double words (32-bits at a time) */

Expand All @@ -267,13 +267,13 @@ bssWords:
rep
stosl /* zero memory per 4 bytes */

#endif /* CONFIG_SSE */
#endif /* CONFIG_X86_SSE */
ret

#ifdef CONFIG_XIP
_x86_data_copy:
/* EDI = dest, ESI = source, ECX = size in 32-bit chunks */
#ifdef CONFIG_SSE
#ifdef CONFIG_X86_SSE
/* copy 16 bytes at a time using XMM until < 16 bytes remain */

movl %ecx ,%edx /* save number of quad bytes */
Expand All @@ -290,22 +290,22 @@ dataDQ:
dataWords:
movl %edx, %ecx /* restore # quad bytes */
andl $0x3, %ecx /* only need to copy at most 3 quad bytes */
#endif /* CONFIG_SSE */
#endif /* CONFIG_X86_SSE */

rep
movsl /* copy data 4 bytes at a time */
ret
#endif /* CONFIG_XIP */


#if defined(CONFIG_SSE)
#if defined(CONFIG_X86_SSE)

/* SSE control & status register initial value */

_sse_mxcsr_default_value:
.long 0x1f80 /* all SSE exceptions clear & masked */

#endif /* CONFIG_SSE */
#endif /* CONFIG_X86_SSE */

/* Interrupt Descriptor Table (IDT) definition */

Expand Down
4 changes: 2 additions & 2 deletions arch/x86/core/ia32/float.c
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Expand Up @@ -145,7 +145,7 @@ static inline void z_do_sse_regs_init(void)
*/
static void FpCtxSave(struct k_thread *thread)
{
#ifdef CONFIG_SSE
#ifdef CONFIG_X86_SSE
if ((thread->base.user_options & K_SSE_REGS) != 0) {
z_do_fp_and_sse_regs_save(&thread->arch.preempFloatReg);
return;
Expand All @@ -163,7 +163,7 @@ static void FpCtxSave(struct k_thread *thread)
static inline void FpCtxInit(struct k_thread *thread)
{
z_do_fp_regs_init();
#ifdef CONFIG_SSE
#ifdef CONFIG_X86_SSE
if ((thread->base.user_options & K_SSE_REGS) != 0) {
z_do_sse_regs_init();
}
Expand Down
14 changes: 7 additions & 7 deletions arch/x86/core/ia32/swap.S
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Expand Up @@ -131,18 +131,18 @@ SECTION_FUNC(TEXT, arch_swap)
* switch.
*/
/* Save outgpoing thread context */
#ifdef CONFIG_SSE
#ifdef CONFIG_X86_SSE
fxsave _thread_offset_to_preempFloatReg(%edx)
fninit
#else
fnsave _thread_offset_to_preempFloatReg(%edx)
#endif
/* Restore incoming thread context */
#ifdef CONFIG_SSE
#ifdef CONFIG_X86_SSE
fxrstor _thread_offset_to_preempFloatReg(%eax)
#else
frstor _thread_offset_to_preempFloatReg(%eax)
#endif /* CONFIG_SSE */
#endif /* CONFIG_X86_SSE */
#elif defined(CONFIG_LAZY_FPU_SHARING)
/*
* Clear the CR0[TS] bit (in the event the current thread
Expand Down Expand Up @@ -206,7 +206,7 @@ SECTION_FUNC(TEXT, arch_swap)
je restoreContext_NoFloatSave


#ifdef CONFIG_SSE
#ifdef CONFIG_X86_SSE
testb $K_SSE_REGS, _thread_offset_to_user_options(%ebx)
je x87FloatSave

Expand All @@ -221,7 +221,7 @@ SECTION_FUNC(TEXT, arch_swap)
jmp floatSaveDone

x87FloatSave:
#endif /* CONFIG_SSE */
#endif /* CONFIG_X86_SSE */

/* 'fnsave' performs an implicit 'fninit' after saving state! */

Expand All @@ -245,7 +245,7 @@ restoreContext_NoFloatSave:
testb $X86_THREAD_FLAG_ALL, _thread_offset_to_flags(%eax)
je restoreContext_NoFloatRestore

#ifdef CONFIG_SSE
#ifdef CONFIG_X86_SSE
testb $K_SSE_REGS, _thread_offset_to_user_options(%eax)
je x87FloatRestore

Expand All @@ -254,7 +254,7 @@ restoreContext_NoFloatSave:

x87FloatRestore:

#endif /* CONFIG_SSE */
#endif /* CONFIG_X86_SSE */

frstor _thread_offset_to_preempFloatReg(%eax)

Expand Down
55 changes: 54 additions & 1 deletion arch/x86/ia32.cmake
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Expand Up @@ -21,7 +21,60 @@ if(CMAKE_C_COMPILER_ID STREQUAL "Clang")
)
endif()

zephyr_cc_option_ifndef(CONFIG_SSE_FP_MATH -mno-sse)
if(CONFIG_X86_MMX)
zephyr_cc_option(-mmmx)
else()
zephyr_cc_option(-mno-mmx)
endif()

if(CONFIG_X86_SSE)
zephyr_cc_option(-msse)

if(CONFIG_X86_SSE_FP_MATH)
zephyr_cc_option(-mfpmath=sse)
else()
zephyr_cc_option(-mfpmath=387)
endif()

if(CONFIG_X86_SSE2)
zephyr_cc_option(-msse2)
else()
zephyr_cc_option(-mno-sse2)
endif()

if(CONFIG_X86_SSE3)
zephyr_cc_option(-msse3)
else()
zephyr_cc_option(-mno-sse3)
endif()

if(CONFIG_X86_SSSE3)
zephyr_cc_option(-mssse3)
else()
zephyr_cc_option(-mno-ssse3)
endif()

if(CONFIG_X86_SSE41)
zephyr_cc_option(-msse4.1)
else()
zephyr_cc_option(-mno-sse4.1)
endif()

if(CONFIG_X86_SSE42)
zephyr_cc_option(-msse4.2)
else()
zephyr_cc_option(-mno-sse4.2)
endif()

if(CONFIG_X86_SSE4A)
zephyr_cc_option(-msse4a)
else()
zephyr_cc_option(-mno-sse4a)
endif()

else()
zephyr_cc_option(-mno-sse)
endif()

if(CMAKE_VERBOSE_MAKEFILE)
set(GENIDT_EXTRA_ARGS --verbose)
Expand Down
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