arch: riscv: common: linker: Add itcm & dtcm sections

[nandojve]

The current riscv linker script don't have sections for Data & Instruction Tightly Coupled Memory. Add itcm and dtcm sections to make it available.

Signed-off-by: Gerson Fernando Budke [email protected]

[katsuster]

@nandojve
Hello. I agreed with your changing policy. We will be happy to use DTCM and ITCM for more faster speed.

My opinion is DTCM and ITCM are implemented on SiFive SoCs, but are they based on some standard of RISC-V arch?
If not, these change should NOT be implemented into common RISC-V arch files (arch/riscv/common). It's better into SoC specific linker script.

[nandojve]

@nandojve
Hello. I agreed with your changing policy. We will be happy to use DTCM and ITCM for more faster speed.

My opinion is DTCM and ITCM are implemented on SiFive SoCs, but are they based on some standard of RISC-V arch?
If not, these change should NOT be implemented into common RISC-V arch files (arch/riscv/common). It's better into SoC specific linker script.

Hi @katsuster ,

This is for a SiFive E24 core with two TCM units of 48k each. Both units can be used for instruction or data and can be combined on a big 96k region, since are continuous.

[cfriedt]

@nandojve, @katsuster -

The concept of TCM is not specific to any architecture.

Just with a quick grep, it looks as though the concepts of itcm / dtcm are not architecture-specific in Zephyr (which is a good thing, and I'm happy to see that). The terminology originates from ARM of course. SiFive actually calls their implementation TIM (tightly-integrated memory).

Sources:

• include/linker/linker-defs.h
• include/linker/sections.h
• include/linker/section_tags.h

Likely the addition did come from ARM / cortex-m though

• include/arch/arm/aarch32/cortex_m/scripts/linker.ld

Given that, I don't see a problem with adding it here as well, or to any other architecture for that matter. I think it was likely defined in an architecture-independent way specifically for this use case.

[cfriedt]

Please increase alignment to 8 bytes to accomodate rv64. Alignment could also eventually be a DT property.

[nandojve]

Just with a quick grep, it looks as though the concepts of itcm / dtcm are not architecture-specific in Zephyr (which is a good thing, and I'm happy to see that). The terminology originates from ARM of course. SiFive actually calls their implementation TIM (tightly-integrated memory).

Yes, names were chosen to be compliant with zephyr,i/dtcm devicetree nodes, for instance:

zephyr/boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts

Lines 25 to 26 in 689864e

	zephyr,itcm = &itcm;
	zephyr,dtcm = &dtcm;

Please increase alignment to 8 bytes to accomodate rv64.

All sections were align to 8 bytes, just to make sure.

[nandojve]

Apply #37484 rename.