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@YuguoWH YuguoWH commented Aug 23, 2021

Adding ARC MPU v3 and v6 support.
The v3 uses same logic with v2 and the only difference is to support 32 bytes minimal region size.
The v6 support 32 bytes, and it can have up to 32 regions. The regions are divided into 2 banks and switched by set/unset RB bit in MPU_EN aux register
This PR also introduces a new nsim hs board simulator which can validate/test with mpu v6.

@YuguoWH YuguoWH requested a review from ruuddw as a code owner August 23, 2021 10:37
@github-actions github-actions bot added area: API Changes to public APIs area: ARC ARC Architecture labels Aug 23, 2021
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YuguoWH commented Aug 23, 2021

related issue #37309

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@abrodkin abrodkin left a comment

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Maybe move common functionality into version-agnostic file and then do specific things in v2 & v6 files to reduce duplication of code?

Also see some minor comments.

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Maybe

#if (CONFIG_ARC_MPU_VER == 4) || (CONFIG_ARC_MPU_VER == 6)

?

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2021 ;)

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ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V6_INTERNAL_H_ (see v6)

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Why mention MPUv2 in code for MPUv6?

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Ditto

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@evgeniy-paltsev evgeniy-paltsev left a comment

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Hi Yuguo,

please find some comments (mostly minor).

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return true;

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return false;

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This one fits in 100 symbol per line limit so let's keep it in one line.

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Hmm, is it really about MPUv2?

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This one fits in 100 symbol per line limit so let's keep it in one line.

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This one fits in 100 symbol per line limit so let's keep it in one line.

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This one fits in 100 symbol per line limit so let's keep it in one line.

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This one fits in 100 symbol per line limit so let's keep it in one line.

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This one fits in 100 symbol per line limit so let's keep it in one line.

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Hmm, Is it correct? We don't have MPU in this NSIM SoC configuration.

@YuguoWH YuguoWH force-pushed the topic-mpu-v6 branch 5 times, most recently from 5e0f2ae to 36ad8bd Compare August 24, 2021 12:56
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@abrodkin abrodkin left a comment

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With a couple of style nitpicks LGTM.

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Frankly I don't like these cryptic numbers. I guess these are some groups of bits shifted left?
Look at BIT_MASK() in https://github.com/zephyrproject-rtos/zephyr/blob/main/include/sys/util_macro.h#L68. Then we'll get something like BIT_MASK(xxx) << yyy which is much more readable.

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Maybe BIT(x) and ~BIT(x) correspondigly?

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BIT(0)?

@abrodkin abrodkin added this to the v2.7.0 milestone Aug 24, 2021
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As we use r_index only in loop probably it's better to define it in loop itself:

for (int r_index = 0; r_index < get_num_regions(); r_index++) {

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I don't think we need to split definition and declaration here. Let's combine it:

/* comment */
int r_index = num_regions - mpu_config.num_regions;

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We don't exceed the Zephyr line limit here (100 symbols per line), please keep it in one line.

Please check rest of the code - we have a lot of places where we can put the whole expression in one line. It improves code readability a lot.

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Ditto.

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Ditto.

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Should we move those magic numbers to some defines / constants?

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I guess it would be enough to also use much simpler understood BIT_MASK(2) & BIT_MASK(3) << 9 here.

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Still It would be better to have all this shift values named. For example we can use "AUX_MPU_REGxx_FIELDxx_SHIFT"

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As we use i only in loop probably it's better to define it in loop itself:

for (uint32_t i = 0U; i < r_index; i++) {

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Ditto.

@YuguoWH YuguoWH force-pushed the topic-mpu-v6 branch 2 times, most recently from 489f934 to 43ac849 Compare August 26, 2021 07:12
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In commit titles it's better to say "add support of" instead of "to".
Also some comments below.

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So you don't like #define AUX_MPU_RDP_ATTR_MASK (BIT_MASK(6) << 3)? ;)

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And here #define AUX_MPU_RDP_SIZE_MASK (BIT_MASK(3) << 9 | BIT_MASK(2))?

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I guess it would be enough to also use much simpler understood BIT_MASK(2) & BIT_MASK(3) << 9 here.

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@YuguoWH could you please also add the nSIM board with v6 MPU so we can easily test it in our verification / manually?

@YuguoWH YuguoWH force-pushed the topic-mpu-v6 branch 2 times, most recently from f943954 to 8cdf600 Compare August 27, 2021 08:59
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With 2 nitpicks LGTM

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Why not use BIT_MASK here as well as in the next line?

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then it would be:
#define AUX_MPU_RDP_REGION_SIZE(size) (((size - 1) & BIT_MASK(2)) | \ (((size - 1) & (BIT_MASK(3) << 2)) << 7))
I think it looks more complex...

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changed

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Ditto

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@YuguoWH looks like it need to be rebased on top of cd87366

Add support of ARC mpu version 3 which can have region size down to 32
bytes

Signed-off-by: Yuguo Zou <[email protected]>
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YuguoWH commented Aug 27, 2021

Hi @evgeniy-paltsev , PR rebased, thanks.

Add support of ARC mpu v6
* minimal region size down to 32 bytes
* maximal region number up to 32
* not support uncacheable region and volatile uncached region
* clean up mpu code for better readablity

Signed-off-by: Yuguo Zou <[email protected]>
We add support of mpu v6 therefore it is needed to have a board to
validate that feature. This commit add a new HS nsim simulator
which supports mpu v6.

Signed-off-by: Yuguo Zou <[email protected]>
@abrodkin abrodkin removed the request for review from IRISZZW August 27, 2021 14:54
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@nashif could you please pick this one up for v2.7?

@nashif nashif merged commit 7d8d4fd into zephyrproject-rtos:main Aug 27, 2021
@YuguoWH YuguoWH deleted the topic-mpu-v6 branch August 30, 2021 06:02
config SOC_NSIM_HS_MPUV6
bool "Synopsys ARC HS with MPU v6 in nSIM"
select CPU_HAS_MPU
select CPU_HAS_FPU
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Why is FPU enabled?

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I keep it same with other NSIM_HS boards, so FPU is enabled

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