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Fix non-standard pseudo-instructions of RISC-V #41147

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Merged
merged 1 commit into from
Feb 4, 2022
Merged

Fix non-standard pseudo-instructions of RISC-V #41147

merged 1 commit into from
Feb 4, 2022

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@henry-hsieh
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@henry-hsieh henry-hsieh commented Dec 14, 2021 •
edited by carlescufi
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Fixes #41100.

@zephyrbot zephyrbot added platform: ESP32 Espressif ESP32 area: RISCV RISCV Architecture (32-bit & 64-bit) platform: ITE ITE labels Dec 14, 2021
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nandojve commented Dec 14, 2021

CC: @soburi

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soburi commented Dec 14, 2021

@nandojve

CC: @soburi

I verified this change works fine with #34970, and no need for an additional patch.
(No jalr instruction in this #34970)

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katsuster commented Jan 18, 2022

@henry-hsieh
CI is cancelled... Please try again to rebase and push.

@henry-hsieh
riscv: fix non-standard assembly of RISC-V
3ec816f 
Non-standard `jalr rd, rs` pseudo-instructions are used.
This commit changes them to `ret` for standard return pseudo-instruction
or `jalr rd, rs, 0` for no offset jump register and link.

Fixes #41100.

Signed-off-by: Henry Hsieh <[email protected]>
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katsuster commented Jan 23, 2022

@henry-hsieh
Thanks!
@cfriedt
I think this PR is ready to merge. Would you check and merge if no problem?

@carlescufi carlescufi merged commit 58d50a0 into zephyrproject-rtos:main Feb 4, 2022
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@jackrosenthal jackrosenthal jackrosenthal approved these changes

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area: RISCV RISCV Architecture (32-bit & 64-bit) platform: ESP32 Espressif ESP32 platform: ITE ITE

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Non-standard RISC-V assembly is used