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Fix non-standard pseudo-instructions of RISC-V #41147

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Merged
merged 1 commit into from
Feb 4, 2022
Merged

Fix non-standard pseudo-instructions of RISC-V #41147

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2 changes: 1 addition & 1 deletion arch/riscv/core/isr.S
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Original file line number Diff line number Diff line change
Expand Up @@ -733,7 +733,7 @@ call_irq:
RV_OP_LOADREG t1, RV_REGSIZE(t0)

/* Call ISR function */
jalr ra, t1
jalr ra, t1, 0

on_thread_stack:
/* Get reference to _kernel */
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2 changes: 1 addition & 1 deletion arch/riscv/core/swap.S
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Expand Up @@ -54,7 +54,7 @@ SECTION_FUNC(exception.other, arch_swap)
addi a0, t2, 0

/* Return */
jalr x0, ra
ret


/*
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2 changes: 1 addition & 1 deletion soc/riscv/esp32c3/soc_irq.S
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Expand Up @@ -20,7 +20,7 @@ SECTION_FUNC(exception.other, __soc_handle_irq)
addi sp, sp,-4
sw ra, 0x00(sp)
la t1, soc_intr_get_next_source
jalr ra, t1
jalr ra, t1, 0
lw ra, 0x00(sp)
addi sp, sp, 4
ret
2 changes: 1 addition & 1 deletion soc/riscv/riscv-ite/common/soc_irq.S
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Expand Up @@ -57,4 +57,4 @@ SECTION_FUNC(exception.other, __soc_is_irq)

not_interrupt:
/* return */
jalr x0, ra
ret
4 changes: 2 additions & 2 deletions soc/riscv/riscv-privilege/common/soc_irq.S
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Expand Up @@ -31,7 +31,7 @@ SECTION_FUNC(exception.other, __soc_handle_irq)
csrrc t1, mip, t0

/* Return */
jalr x0, ra
ret

/*
* __soc_is_irq is defined as .weak to allow re-implementation by
Expand All @@ -58,4 +58,4 @@ SECTION_FUNC(exception.other, __soc_is_irq)

not_interrupt:
/* return */
jalr x0, ra
ret
2 changes: 1 addition & 1 deletion soc/riscv/riscv-privilege/neorv32/soc_irq.S
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Expand Up @@ -25,4 +25,4 @@ SECTION_FUNC(exception.other, __soc_handle_irq)
csrrs t2, mie, t1

/* Return */
jalr x0, ra
ret