Add initial pinctrl implementation for RT1062

dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml

@@ -0,0 +1,137 @@
+# Copyright (c) 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree. These
+  nodes can be autogenerated using the MCUXpresso config tools combined with
+  the rt_dts_gen.py script in NXP's HAL.
+  Each pinctrl node simply selects the pinmux setting by default, sets all
+  configuration values to reset values for the SOC register. Individual
+  overrides to pinctrl nodes can be applied at the board level.
+
+  for example, here is an override for the GPIO_AD_B0_12 pad:
+
+  &IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL {
+      bias-pull-up = <2>;
+      drive-strength = <7>;
+      nxp,speed = <3>;
+      slew-rate = <1>;
+  }
+
+  This will select GPIO_AD_B0_12 for use as SCL on LPI2C4, and enable
+  the 100K pull up resistor on the pin. It will also increase the slew rate
+  and drive strength to their maximum settings. Note that the soc level pinctrl
+  DTSI file can be examined to find the soc level defaults for this pinmux
+  setting.
+
+  The pinmux property itself is used to make the MUX selection that
+  pinctrl node will apply.
+
+  Here are the affects of each property on the IOMUXC SW_PAD_CTL register:
+
+  input-schmitt-enable: HYS=1
+  drive-open-drain: ODE=1
+  input-enable: SION=1 (in SW_MUX_CTL_PAD register)
+  bias-bus-hold: PKE=1, PUE=0
+  bias-pull-down: PKE=1, PUE=1, PUS=0
+  bias-pull-up: PKE=1, PUE=1, PUS=<prop_value>
+  slew-rate: SRE=<prop_value>
+  drive-strength: DSE=<prop_value>
+  nxp,speed: SPEED=<prop_value>
+
+
+
+compatible: "nxp,mcux-rt-pinctrl"
+
+include:
+    - name: base.yaml
+    - name: pincfg-node.yaml
+      child-binding:
+        property-allowlist:
+          - input-schmitt-enable
+          - drive-open-drain
+          - input-enable
+          - bias-bus-hold
+          - bias-pull-down
+
+properties:
+    reg:
+      required: true
+
+child-binding:
+  description: |
+    MCUX RT pin controller pin configuration node.
+  properties:
+    pinmux:
+      required: true
+      type: array
+      description: |
+        An array of values defining the configuration register for a given
+        pinmux mode. See fsl_iomuxc.h in the NXP HAL for a list.
+        The array takes the following format:
+        mux_register, mux_value, input_register, input_daisy, config_register
+    drive-strength:
+      required: false
+      type: int
+      default: 0
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+        - 4
+        - 5
+        - 6
+        - 7
+      description: |
+        Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
+        000 DSE_0_output_driver_disabled_ — output driver disabled
+        001 DSE_1_R0_1 — 157 Ohm impedance @3.3V, 260 Ohm impedance @1.8V
+        010 DSE_2_R0_2 — 78 Ohm @3.3V, 130 Ohm @1.8V
+        011 DSE_3_R0_3 — 53 Ohm @3.3V, 88 Ohm @1.8V
+        100 DSE_4_R0_4 — 39 Ohm @3.3V, 65 Ohm @1.8V
+        101 DSE_5_R0_5 — 32 Ohm @3.3V, 52 Ohm @1.8V
+        110 DSE_6_R0_6 — 32 Ohm @3.3V, 43 Ohm @1.8V
+        111 DSE_7_R0_7 — 26 Ohm @3.3V, 37 Ohm @1.8V
+    bias-pull-up:
+      required: false
+      type: int
+      default: 0
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+      description: |
+        Select the value of the pull up resistor present on this pin
+        Corresponds to the PUS field in the IOMUXC peripheral
+        00 Unused- no change will be applied to pin
+        01 PUS_1_47K_Ohm_Pull_Up — 47K Ohm Pull Up
+        10 PUS_2_100K_Ohm_Pull_Up — 100K Ohm Pull Up
+        11 PUS_3_22K_Ohm_Pull_Up — 22K Ohm Pull Up
+    slew-rate:
+      required: false
+      type: int
+      default: 0
+      enum:
+        - 0
+        - 1
+      description: |
+        Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
+        0 SRE_0_Slow_Slew_Rate — Slow Slew Rate
+        1 SRE_1_Fast_Slew_Rate — Fast Slew Rate
+    nxp,speed:
+      required: false
+      type: int
+      default: 0
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+      description: |
+        Sets pin speed. Corresponds to SPEED field in IOMUXC peripheral
+        00 SPEED_0_low_50MHz_ — low(50MHz)
+        01 SPEED_1_medium_100MHz_ — medium(100MHz)
+        10 SPEED_2_medium_100MHz_ — medium(100MHz)
+        11 SPEED_3_max_200MHz_ — max(200MHz)