soc: arm: atmel: implement SAM V70 support

drivers/can/Kconfig.sam

@@ -8,3 +8,15 @@ config CAN_SAM
 	bool "Atmel SAM CAN driver"
 	default $(dt_compat_enabled,$(DT_COMPAT_ATMEL_SAM_CAN))
 	select CAN_MCAN
+
+if CAN_SAM
+
+config CAN_MAX_FILTER
+	int "Maximum number of concurrent active filters"
+	default 5
+	range 1 32
+	help
+	  Defines the array size of the callback/msgq pointers.
+	  Must be at least the size of concurrent reads.
+
+endif # CAN_SAM

drivers/ethernet/Kconfig.sam_gmac

@@ -5,7 +5,7 @@
 
 menuconfig ETH_SAM_GMAC
 	bool "Atmel SAM Ethernet driver"
-	depends on SOC_FAMILY_SAM0 || SOC_FAMILY_SAM
+	depends on (SOC_FAMILY_SAM0 || SOC_FAMILY_SAM) && !SOC_SERIES_SAMV70
 	select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
 	select MDIO
 	help

drivers/flash/Kconfig.sam

@@ -10,6 +10,6 @@ config SOC_FLASH_SAM
 	select FLASH_HAS_DRIVER_ENABLED
 	select MPU_ALLOW_FLASH_WRITE if ARM_MPU
 	depends on SOC_SERIES_SAME70 || \
-		   SOC_SERIES_SAMV71
+		   SOC_SERIES_SAMV71 || SOC_SERIES_SAMV70
 	help
 	  Enable the Atmel SAM series internal flash driver.

soc/arm/atmel_sam/samv70/CMakeLists.txt

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+  soc_config.c
+  )

soc/arm/atmel_sam/samv70/Kconfig.defconfig.series

@@ -0,0 +1,71 @@
+# Atmel SAM V70 MCU series configuration options
+
+# Copyright (c) 2019 Gerson Fernando Budke
+# Copyright (c) 2016 Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_SAMV70
+
+config SOC_SERIES
+	default "samv70"
+
+config SOC_PART_NUMBER
+	default "samv70q20" if SOC_PART_NUMBER_SAMV70Q20
+	default "samv70q19" if SOC_PART_NUMBER_SAMV70Q19
+	default "samv70n20" if SOC_PART_NUMBER_SAMV70N20
+	default "samv70n19" if SOC_PART_NUMBER_SAMV70N19
+	default "samv70j20" if SOC_PART_NUMBER_SAMV70J20
+	default "samv70j19" if SOC_PART_NUMBER_SAMV70J19
+	default "samv70q20b" if SOC_PART_NUMBER_SAMV70Q20B
+	default "samv70q19b" if SOC_PART_NUMBER_SAMV70Q19B
+	default "samv70n20b" if SOC_PART_NUMBER_SAMV70N20B
+	default "samv70n19b" if SOC_PART_NUMBER_SAMV70N19B
+	default "samv70j20b" if SOC_PART_NUMBER_SAMV70J20B
+	default "samv70j19b" if SOC_PART_NUMBER_SAMV70J19B
+
+#
+# SAM V70 family has in total 71 peripherals capable of generating interrupts
+# for the revision A and 74 for the revision B (not all Peripheral Identifiers
+# are used).
+#
+config NUM_IRQS
+	default 74 if SOC_ATMEL_SAMV70_REVB
+	default 71
+
+# Configure default device drivers. If a feature is supported by more than one
+# device driver the default configuration will be placed in the board defconfig
+# file.
+
+config DMA_SAM_XDMAC
+	default y
+	depends on DMA
+
+config ADC_SAM_AFEC
+	default y
+	depends on ADC
+
+config I2C_SAM_TWIHS
+	default y
+	depends on I2C
+
+config I2S_SAM_SSC
+	default y
+	depends on I2S
+
+config USB_DC_SAM_USBHS
+	default y
+	depends on USB_DEVICE_DRIVER
+
+config ENTROPY_SAM_RNG
+	default y
+	depends on ENTROPY_GENERATOR
+
+config SOC_FLASH_SAM
+	default y
+	depends on FLASH
+
+config PWM_SAM
+	default y
+	depends on PWM
+
+endif # SOC_SERIES_SAMV70

soc/arm/atmel_sam/samv70/Kconfig.series

@@ -0,0 +1,22 @@
+# Atmel SAM V70 MCU series
+
+# Copyright (c) 2019 Gerson Fernando Budke
+# Copyright (c) 2016 Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_SAMV70
+	bool "Atmel SAMV70 MCU"
+	select ARM
+	select CPU_CORTEX_M7
+	select SOC_FAMILY_SAM
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select CPU_CORTEX_M_HAS_CACHE
+	select CPU_CORTEX_M_HAS_DWT
+	select ASF
+	select XIP
+	select CPU_HAS_ARM_MPU
+	select HAS_SWO
+	help
+	  Enable support for Atmel SAM V70 ARM Cortex-M7 Microcontrollers.
+	  Part No.: SAMV70J19, SAMV70J20, SAMV70N19, SAMV70N20, SAMV70Q19, SAMV70Q20,
+	  SAMV70J19B, SAMV70J20B, SAMV70N19B, SAMV70N20B, SAMV70Q19B, SAMV70Q20B

soc/arm/atmel_sam/samv70/Kconfig.soc

@@ -0,0 +1,147 @@
+# Atmel SAM V70 MCU series
+
+# Copyright (c) 2019 Gerson Fernando Budke
+# Copyright (c) 2016 Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "Atmel SAMV70 MCU Selection"
+	depends on SOC_SERIES_SAMV70
+
+	config SOC_PART_NUMBER_SAMV70Q20
+		bool "SAMV70Q20"
+
+	config SOC_PART_NUMBER_SAMV70Q19
+		bool "SAMV70Q19"
+
+	config SOC_PART_NUMBER_SAMV70N20
+		bool "SAMV70N20"
+
+	config SOC_PART_NUMBER_SAMV70N19
+		bool "SAMV70N19"
+
+	config SOC_PART_NUMBER_SAMV70J20
+		bool "SAMV70J20"
+
+	config SOC_PART_NUMBER_SAMV70J19
+		bool "SAMV70J19"
+
+	config SOC_PART_NUMBER_SAMV70Q20B
+		bool "SAMV70Q20B"
+		select SOC_ATMEL_SAMV70_REVB
+
+	config SOC_PART_NUMBER_SAMV70Q19B
+		bool "SAMV70Q19B"
+		select SOC_ATMEL_SAMV70_REVB
+
+	config SOC_PART_NUMBER_SAMV70N20B
+		bool "SAMV70N20B"
+		select SOC_ATMEL_SAMV70_REVB
+
+	config SOC_PART_NUMBER_SAMV70N19B
+		bool "SAMV70N19B"
+		select SOC_ATMEL_SAMV70_REVB
+
+	config SOC_PART_NUMBER_SAMV70J20B
+		bool "SAMV70J20B"
+		select SOC_ATMEL_SAMV70_REVB
+
+	config SOC_PART_NUMBER_SAMV70J19B
+		bool "SAMV70J19B"
+		select SOC_ATMEL_SAMV70_REVB
+endchoice
+
+if SOC_SERIES_SAMV70
+
+config SOC_ATMEL_SAMV70_REVB
+	bool
+
+config SOC_ATMEL_SAMV70_EXT_SLCK
+	bool "Use external crystal oscillator for slow clock"
+	help
+	  Say y if you want to use external 32 kHz crystal
+	  oscillator to drive the slow clock. Note that this
+	  adds a few seconds to boot time, as the crystal
+	  needs to stabilize after power-up.
+
+	  Says n if you do not need accurate and precise timers.
+	  The slow clock will be driven by the internal fast
+	  RC oscillator running at 32 kHz.
+
+config SOC_ATMEL_SAMV70_EXT_MAINCK
+	bool "Use external crystal oscillator for main clock"
+	help
+	  The main clock is being used to drive the PLL, and
+	  thus driving the processor clock.
+
+	  Say y if you want to use external crystal oscillator
+	  to drive the main clock. Note that this adds about
+	  a second to boot time, as the crystal needs to
+	  stabilize after power-up.
+
+	  The crystal used here can be from 3 to 20 MHz.
+
+	  Says n here will use the internal fast RC oscillator
+	  running at 12 MHz.
+
+config SOC_ATMEL_SAMV70_MDIV
+	int "MDIV"
+	default 2
+	range 1 4
+	help
+	  This divisor defines a ratio between processor clock (HCLK)
+	  and master clock (MCK):
+	  MCK = HCLK / MDIV
+
+config SOC_ATMEL_SAMV70_PLLA_MULA
+	int "PLL MULA"
+	default 24
+	range 1 62
+	help
+	  This is the multiplier MULA used by the PLL.
+	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
+
+	  Board config file can override this settings
+	  for a particular board.
+
+	  Setting MULA=0 would disable PLL at boot, this is currently
+	  not supported.
+
+	  With default of MULA == 24, and DIVA == 1,
+	  PLL is running at 25 times the main clock frequency.
+
+config SOC_ATMEL_SAMV70_PLLA_DIVA
+	int "PLL DIVA"
+	default 1
+	range 1 255
+	help
+	  This is the divider DIVA used by the PLL.
+	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
+
+	  Board config file can override this settings
+	  for a particular board.
+
+	  Setting DIVA=0 would disable PLL at boot, this is currently
+	  not supported.
+
+	  With default of MULA == 24, and DIVA == 1,
+	  PLL is running at 25 times the main clock frequency.
+
+config SOC_ATMEL_SAMV70_WAIT_MODE
+	bool "Go to Wait mode instead of Sleep mode"
+	depends on SOC_ATMEL_SAMV70_EXT_MAINCK
+	default y if DEBUG
+	help
+	  For JTAG debugging CPU clock (HCLK) should not stop. In order
+	  to achieve this, make CPU go to Wait mode instead of Sleep
+	  mode while using external crystal oscillator for main clock.
+
+config SOC_ATMEL_SAMV70_DISABLE_ERASE_PIN
+	bool "Disable ERASE pin"
+	help
+	  At reset ERASE pin is configured in System IO mode. Asserting the ERASE
+	  pin at '1' will completely erase Flash memory. Setting this option will
+	  switch the pin to general IO mode giving control of the pin to the GPIO
+	  module.
+
+endif # SOC_SERIES_SAMV70

soc/arm/atmel_sam/samv70/linker.ld

@@ -0,0 +1,8 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>