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Adds support for the CVA6 CPU on a GenesysII FPGA board (https://github.com/openhwgroup/cva6).
The SoC currently contains the CVA6 CPU in 64-bit configuration with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the lowRISC ethernet subsystem.

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as per other pr

Adds support for the CVA6 CPU on a GenesysII FPGA board
(https://github.com/openhwgroup/cva6).
The SoC currently contains the CVA6 CPU in 64-bit configuration with the
SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for
booting from SD, a boot ROM, and I2C controller for on-board audio, a
GPIO and the lowRISC ethernet subsystem.

Signed-off-by: Eric Ackermann <[email protected]>
@WorldofJARcraft
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Merged into #77732

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2 participants