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@nono313 nono313 commented Sep 8, 2024

Implementing PLL fracn register for STM32H7 based on what is currently implemented for STM32U5 series.

add fracn to STM32H7 pll clock binding

Signed-off-by: Nathan Olff <[email protected]>
use fracn value if defined for each PLL 1, 2 and 3 based on stm32u5 code

Signed-off-by: Nathan Olff <[email protected]>
remove check for system clock frequency in clock_stm32_ll_h7 because of
addition of fracn (difficult to handle)

Signed-off-by: Nathan Olff <[email protected]>
@nono313 nono313 changed the title draft: Fracn on stm32h7 Fracn on stm32h7 Sep 9, 2024
@nono313 nono313 marked this pull request as ready for review September 9, 2024 11:44
@nono313 nono313 changed the title Fracn on stm32h7 drivers: clock_control: implement fracn for pll on stm32h7 Sep 10, 2024
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@erwango erwango left a comment

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Otherwise LGTM

add overlay to use fracn with HSI in clock configuration tests for
stm32h7

Signed-off-by: Nathan Olff <[email protected]>
@carlescufi carlescufi merged commit eb3f718 into zephyrproject-rtos:main Sep 16, 2024
@nono313 nono313 deleted the fracn-on-stm32h7 branch September 17, 2024 07:18
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6 participants