TI MSPM0 Support

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g1106.dtsi

@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi>
+#include <ti/mspm0g1x0x_g3x0x/mspm0gxxx6.dtsi>

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g1107.dtsi

@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi>
+#include <ti/mspm0g1x0x_g3x0x/mspm0gxxx7.dtsi>

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g1506.dtsi

@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi>
+#include <ti/mspm0g1x0x_g3x0x/mspm0gxxx6.dtsi>

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g1507.dtsi

@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi>
+#include <ti/mspm0g1x0x_g3x0x/mspm0gxxx7.dtsi>

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi

@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <arm/armv6-m.dtsi>
+#include <freq.h>
+#include <zephyr/dt-bindings/clock/mspm0_clock.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m0+";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20200000 {
+		compatible = "mmio-sram";
+	};
+
+	flash0: serial-flash@0 {
+		compatible = "serial-flash";
+	};
+
+	sysclk: system-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <DT_FREQ_M(32)>;
+		#clock-cells = <0>;
+	};
+
+	clkmux: clock-controller {
+		compatible = "ti,mspm0-clock-mux";
+		mclk-div = <1>;
+		uclk-div = <1>;
+		#clock-cells = <1>;
+	};
+
+	clocks: clocks {
+		sysosc: sysosc {
+			compatible = "ti,mspm0-oscillator";
+			clock-frequency = <DT_FREQ_M(32)>;
+			#clock-cells = <0>;
+		};
+
+		lfosc: lfosc {
+			compatible = "fixed-clock";
+			clock-frequency = <32678>;
+			#clock-cells = <0>;
+		};
+
+		pll: pll {
+			compatible = "ti,mspm0-pll";
+			clocks = <&sysosc 0>;
+			p-div = <2>;
+			q-div = <5>;
+			clk1-div = <2>;
+			clk2x-div = <2>;
+			#clock-cells = <0>;
+			status = "okay";
+		};
+	};
+
+	soc {
+
+		pinctrl: pin-controller@400a0000{
+			compatible = "ti,mspm0-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x400a0000 0x4000>;
+
+			gpioa: gpio@400a0000 {
+				compatible = "ti,mspm0-gpio";
+				reg = <0x400a0000 0x2000>;
+				interrupts = <1 0>;
+				status = "disabled";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpiob: gpio@400a2000 {
+				compatible = "ti,mspm0-gpio";
+				reg = <0x400a2000 0x2000>;
+				interrupts = <1 0>;
+				status = "disabled";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		uart0: uart@40108000 {
+			compatible = "ti,mspm0-uart";
+			reg = <0x40108000 0x2000>;
+			interrupts = <15 0>;
+			current-speed = <115200>;
+			clocks = <&clkmux MSPM0_CLOCK_BUS_ULPCLK>;
+			status = "disabled";
+		};
+
+		uart1: uart@40100000 {
+			compatible = "ti,mspm0-uart";
+			reg = <0x40100000 0x2000>;
+			interrupts = <13 0>;
+			current-speed = <115200>;
+			clocks = <&clkmux MSPM0_CLOCK_BUS_ULPCLK>;
+			status = "disabled";
+		};
+
+		uart2: uart@40102000 {
+			compatible = "ti,mspm0-uart";
+			reg = <0x40102000 0x2000>;
+			interrupts = <14 0>;
+			current-speed = <115200>;
+			clocks = <&clkmux MSPM0_CLOCK_BUS_ULPCLK>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <2>;
+};

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g3106.dtsi

@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi>
+#include <ti/mspm0g1x0x_g3x0x/mspm0gxxx6.dtsi>

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g3107.dtsi

@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi>
+#include <ti/mspm0g1x0x_g3x0x/mspm0gxxx7.dtsi>

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g3506.dtsi

@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi>
+#include <ti/mspm0g1x0x_g3x0x/mspm0gxxx6.dtsi>

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g3507.dtsi

@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi>
+#include <ti/mspm0g1x0x_g3x0x/mspm0gxxx7.dtsi>

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0gxxx6.dtsi

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <mem.h>
+#include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi>
+
+/ {
+	sram0: memory@20200000 {
+		reg = <0x20200000 DT_SIZE_K(32)>;
+	};
+
+	flash0: serial-flash@0 {
+		reg = <0x0 DT_SIZE_K(64)>;
+	};
+};

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0gxxx7.dtsi

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <mem.h>
+#include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi>
+
+/ {
+	sram0: memory@20200000 {
+		reg = <0x20200000 DT_SIZE_K(32)>;
+	};
+
+	flash0: serial-flash@0 {
+		reg = <0x0 DT_SIZE_K(128)>;
+	};
+};

dts/bindings/clock/ti,mspm0-clock-mux.yaml

@@ -0,0 +1,43 @@
+# Copyright (c) 2024 Texas Instruments Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI MSPM0 Clock Mux
+
+compatible: "ti,mspm0-clock-mux"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  "#clock-cells":
+    const: 1
+
+  uclk-div:
+    type: int
+    default: 1
+    description: |
+      Divider from MCLK (system clock) to ULPCLK (low power clock). ULPCLK must
+      be less than or equal to 40 MHz. Valid value is 1 when sourced from SYSOSC
+      or LFOSC. Valid values are 1 or 2 when sourced from a high speed clock
+      (such as PLL or external clock).
+
+  mclk-div:
+    type: int
+    default: 1
+    description: |
+      Divider for MCLK (system clock) only when source with SYSOSC with a
+      frequency value of 4 MHz. Disabled otherwise. Valid values are 1-16.
+
+  clock-source:
+    type: phandle
+    required: true
+    description: |
+      Clock Source for the system clock
+
+  clock-frequency:
+    required: true
+    type: int
+    description: |
+      default frequency in Hz for clock output
+
+clock-cells:
+  - bus

dts/bindings/clock/ti,mspm0-oscillator.yaml

@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Texas Instruments Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI MSPM0 Oscillator
+
+compatible: "ti,mspm0-oscillator"
+
+include: [fixed-clock.yaml]
+
+properties:
+  clock-frequency:
+    type: int
+    required: true

dts/bindings/clock/ti,mspm0-pll.yaml

@@ -0,0 +1,56 @@
+# Copyright (c) 2024 Texas Instruments Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI MSPM0 Phase Locked Loop
+
+compatible: "ti,mspm0-pll"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  clocks:
+    required: true
+    description: |
+      Clock reference source
+
+  "#clock-cells":
+    const: 0
+
+  p-div:
+    type: int
+    required: true
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+    description: |
+      pdiv is the pre-divider of the output. ref_in / pdiv * qdiv = VCO
+
+  q-div:
+    type: int
+    required: true
+    description: |
+      qdiv functions as a multiplier value for the ref_in / pdiv * qdiv = VCO
+      Valid Range: 2 - 128
+
+  clk0-div:
+    type: int
+    description: |
+      CLK0 PLL output is only enabled if the divider is present. Use CLK0 on
+      the MSPM0 to output to the MCLK, UCLK, and CPUCLK
+      Valid Range: 1 - 16
+
+  clk1-div:
+    type: int
+    description: |
+      CLK1 PLL output is only enabled if the divider is present. Use CLK1 on
+      the MSPM0 to output to the CANCLK, FCC, or output via EXCLK
+      Valid Range: 1 - 16
+
+  clk2x-div:
+    type: int
+    description: |
+      CLK2X PLL output is only enabled if the divider is present. Use CLK2X on
+      the MSPM0 to output to the MCLK, UCLK, and CPUCLK instead of CLK0
+      Valid Range: 1 - 16

include/zephyr/dt-bindings/clock/mspm0_clock.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright 2024 Texas Instruments Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MSPM0_CLOCK_H
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MSPM0_CLOCK_H
+
+/* Clock bus references */
+#define MSPM0_CLOCK_BUS_BUSCLK
+
+#define MSPM0_CLOCK_BUS_LFCLK  (0x02)
+#define MSPM0_CLOCK_BUS_MFCLK  (0x04)
+#define MSPM0_CLOCK_BUS_ULPCLK (0x18)
+#define MSPM0_CLOCK_BUS_MCLK   (0x28)
+#define MSPM0_CLOCK_BUS_MFPCLK (0x50)
+#define MSPM0_CLOCK_BUS_CANCLK (0x51)
+
+#define MSPM0_CLOCK_SEL_MASK (0x0E)
+
+#define MSPM0_CLOCK_PRESCALE_DIV_1 (0)
+#define MSPM0_CLOCK_PRESCALE_DIV_2 (1)
+#define MSPM0_CLOCK_PRESCALE_DIV_3 (2)
+#define MSPM0_CLOCK_PRESCALE_DIV_4 (3)
+#define MSPM0_CLOCK_PRESCALE_DIV_5 (4)
+#define MSPM0_CLOCK_PRESCALE_DIV_6 (5)
+#define MSPM0_CLOCK_PRESCALE_DIV_7 (6)
+#define MSPM0_CLOCK_PRESCALE_DIV_8 (7)
+
+#define MSPM0_PRESCALE_MASK 0x07
+
+#endif

include/zephyr/dt-bindings/pinctrl/mspm0-pinctrl.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2024 Texas Instruments
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _MSPM0_DT_BINDINGS_PINCTRL_H_
+#define _MSPM0_DT_BINDINGS_PINCTRL_H_
+
+#define MSP_PORT_INDEX_BY_NAME(x) ((x == "PORTA") ? 0 : 1)
+
+/* creates a concatination of the correct pin function based on the CM
+ * and the function suffix. Will evaluate to the pin function number above.
+ */
+
+#define MSPM0_PIN_FUNCTION_ANALOG (0x00000000)
+#define MSPM0_PIN_FUNCTION_GPIO   (0x00000001)
+#define MSPM0_PIN_FUNCTION_2      (0x00000002)
+#define MSPM0_PIN_FUNCTION_3      (0x00000003)
+#define MSPM0_PIN_FUNCTION_4      (0x00000004)
+#define MSPM0_PIN_FUNCTION_5      (0x00000005)
+#define MSPM0_PIN_FUNCTION_6      (0x00000006)
+#define MSPM0_PIN_FUNCTION_7      (0x00000007)
+#define MSPM0_PIN_FUNCTION_8      (0x00000008)
+#define MSPM0_PIN_FUNCTION_9      (0x00000009)
+#define MSPM0_PIN_FUNCTION_10     (0x0000000A)
+
+#define MSP_PINMUX(pincm, function) (((pincm - 1) << 0x10) | function)
+
+#endif