TI MSPM0 Support #79673

JFMSP · 2024-10-10T18:45:03Z

This is a continuation and re-opening of the previous PR #68503. All comments on that PR should be addressed at this point.

I apologize for the delay in getting this PR out, but I am able to respond to comments and would like your help to get this merged.

-JFMSP

zephyrbot · 2024-10-10T18:46:00Z

The following west manifest projects have changed revision in this Pull Request:

Name	Old Revision	New Revision	Diff
hal_ti	zephyrproject-rtos/hal_ti@`2e7b95a`	zephyrproject-rtos/hal_ti#51	zephyrproject-rtos/hal_ti#51/files

Additional metadata changed:

Name	URL	Submodules	West cmds	`module.yml`
hal_ti				✏

⛔ DNM label due to: 1 project with PR revision and 1 project with metadata changes

Note: This message is automatically posted and updated by the Manifest GitHub Action.

github-actions · 2024-10-10T18:52:51Z

Hello @JFMSP, and thank you very much for your first pull request to the Zephyr project!
Our Continuous Integration pipeline will execute a series of checks on your Pull Request commit messages and code, and you are expected to address any failures by updating the PR. Please take a look at our commit message guidelines to find out how to format your commit messages, and at our contribution workflow to understand how to update your Pull Request. If you haven't already, please make sure to review the project's Contributor Expectations and update (by amending and force-pushing the commits) your pull request if necessary.
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boards/ti/lp_mspm0g3507/lp_mspm0g3507_mspm0g3507_defconfig

Changes addressed

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x-pinctrl.dtsi

Ayush1325 · 2024-12-24T05:09:07Z

Is there a reson why mspm0l1105 is missing? Just wondering if it Zephyr was not usable with 32k of ram or if it just wasn't a priority.

Ayush1325 · 2025-01-08T07:39:53Z

@JFMSP any updates.

JFMSP · 2025-01-16T23:14:54Z

Is there a reson why mspm0l1105 is missing? Just wondering if it Zephyr was not usable with 32k of ram or if it just wasn't a priority.

Hey Ayush, MSPM0L1105 has 32kB of Flash. It has 4kB of RAM

Ayush1325 · 2025-01-17T11:35:16Z

Is there a reson why mspm0l1105 is missing? Just wondering if it Zephyr was not usable with 32k of ram or if it just wasn't a priority.

Hey Ayush, MSPM0L1105 has 32kB of Flash. It has 4kB of RAM

Sorry for the misstype. It seems it really is because of RAM, at least from discord conversation. It would be nice if there was some way to have Zephyr on it. Upcoming Pocketbeagle2 has an mspm0l1105.

nordicjm

Apply comments to every commit in this PR, they might have only been raised on some or one instance of the error

nordicjm · 2025-01-20T13:47:44Z

soc/ti/mspm0/mspm0g1x0x_g3x0x/CMakeLists.txt

Suggested change

if(CONFIG_SOC_MSPM0G1106)

zephyr_compile_definitions(-D__MSPM0G1106__)

endif()

if(CONFIG_SOC_MSPM0G1107)

zephyr_compile_definitions(-D__MSPM0G1107__)

endif()

if(CONFIG_SOC_MSPM0G1506)

zephyr_compile_definitions(-D__MSPM0G1506__)

endif()

if(CONFIG_SOC_MSPM0G1507)

zephyr_compile_definitions(-D__MSPM0G1507__)

endif()

if(CONFIG_SOC_MSPM0G3106)

zephyr_compile_definitions(-D__MSPM0G3106__)

endif()

if(CONFIG_SOC_MSPM0G3107)

zephyr_compile_definitions(-D__MSPM0G3107__)

endif()

if(CONFIG_SOC_MSPM0G3506)

zephyr_compile_definitions(-D__MSPM0G3506__)

endif()

if(CONFIG_SOC_MSPM0G3507)

zephyr_compile_definitions(-D__MSPM0G3507__)

endif()

if(CONFIG_SOC_MSPM0G1106)

zephyr_compile_definitions(-D__MSPM0G1106__)

elseif(CONFIG_SOC_MSPM0G1107)

zephyr_compile_definitions(-D__MSPM0G1107__)

elseif(CONFIG_SOC_MSPM0G1506)

...

looks like a requirement for HAL? If so please, push this into modules/hal...

soc/ti/mspm0/mspm0g1x0x_g3x0x/Kconfig.defconfig

nordicjm · 2025-01-20T13:48:39Z

soc/ti/mspm0/mspm0g1x0x_g3x0x/soc.c

use soc hooks

nordicjm · 2025-01-20T13:48:52Z

soc/ti/mspm0/mspm0g1x0x_g3x0x/soc.h

why is clang format disabled?

nordicjm · 2025-01-20T13:49:23Z

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi

Suggested change

nordicjm · 2025-01-20T13:58:39Z

drivers/serial/uart_mspm0.c

nordicjm · 2025-01-20T13:59:08Z

drivers/serial/uart_mspm0.c

defines to top of file

nordicjm · 2025-01-20T13:59:32Z

boards/ti/lp_mspm0g3507/docs/index.rst

Suggested change

Zephyr uses the ``lp_mspm0g3507`` board configuration for building

Zephyr uses the ``lp_mspm0g3507`` board for building

nordicjm · 2025-01-20T13:59:40Z

boards/ti/lp_mspm0g3507/docs/index.rst

not fixed??

The Zephyr ``lp_mspm0g3507`` board supports the...

nordicjm · 2025-01-20T14:00:46Z

boards/ti/lp_mspm0g3507/lp_mspm0g3507.dts

inconsistent spacing

JFMSP · 2025-01-21T21:39:53Z

#79673 (comment)

I don't know why I can't reply in the conversation itself, but I'm assuming @nordicjm that by "fixed" you mean following the format lp_mspm0g3507/mspm0g3507 of board/silicon like that.

After talking with some other members at TI and @parthitce, TI only plans to support the mspm0g3507 silicon with the LP_MSPM0G3507 board, and so there should be a direct 1:1 mapping of board to silicon, as other devices would not share that board name. We don't tend to support new silicon parts on existing boards, as we'd rename them.

I know this changes our flexibility story currently, but I don't see it being an issue with our roadmap.

Added initial SOC support for TI MSPM0 family Signed-off-by: Jackson Farley <[email protected]>

added TI MSPM0 device support to the devicetree Signed-off-by: Jackson Farley <[email protected]>

added pinctrl data for TI MSPM0 Family Signed-off-by: Jackson Farley <[email protected]>

added clock_control support for TI MSPM0 Family Signed-off-by: Jackson Farley <[email protected]>

added pinctrl driver support for MSPM0 Family Signed-off-by: Jackson Farley <[email protected]>

Added GPIO driver support for TI MSPM0 family Signed-off-by: Jackson Farley <[email protected]>

added the Serial (uart) driver for MSPM0 family Signed-off-by: Jackson Farley <[email protected]>

added Texas Instruments LP_MSPM0G3507 launchpad Signed-off-by: Jackson Farley <[email protected]>

nordicjm

You've re-requested my review, so I go and look through to find basically none of the parts I left have been addressed? Fix them ?

nordicjm · 2025-02-03T08:51:27Z

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi

+	};
+
+	soc {
+


Suggested change

nordicjm · 2025-02-03T08:51:55Z

dts/bindings/clock/ti,mspm0-clock-mux.yaml

Not addressed

nordicjm · 2025-02-03T08:52:10Z

dts/bindings/clock/ti,mspm0-clock-mux.yaml

+    required: true
+    type: int
+    description: |
+      default frequency in Hz for clock output


Suggested change

default frequency in Hz for clock output

Default frequency in Hz for clock output

nordicjm · 2025-02-03T08:52:36Z

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x-pinctrl.dtsi

Not addressed

nordicjm · 2025-02-03T08:52:50Z

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x-pinctrl.dtsi

Not addressed

nordicjm · 2025-02-03T08:53:00Z

dts/arm/ti/mspm0g1x0x_g3x0x/mspm0g3xxx-pinctrl.dtsi

+#include <dt-bindings/pinctrl/mspm0-pinctrl.h>
+
+&pinctrl {
+


Suggested change

gmarull

stopped reviewing after observing some major flaws, please, fix them (also check some other drivers as a reference) and re-request review.

gmarull · 2025-02-03T08:56:46Z

boards/ti/lp_mspm0g3507/docs/index.rst

+This section shows how to debug the MSPM0G3507 LaunchPad board using `CCS IDE`_. More information
+on debugging using CCS can be found in `CCS User's Guide`_.
+
+In general, the steps for debugging in CCS are:
+
+   1. Open CCS
+   2. Go to :menuselection:`Window --> Show View --> Target Configruation`
+   3. Import target confguration by right clicking User Defined, selecting Import target configuration and pointing to the lp_mspm0g3507/support/MSPM0G3507.ccxml
+   4. Launch target configuration by right clicking the new MSPM0G3507.ccxml file and clicking Launch target configuration
+   5. Plug in the device and connect to it by going to :menuselection:`Run --> Connect Target`
+   6. Go to :menuselection:`Run --> Load --> Load Symbols and load in the zephyr.elf file loaded`
+   7. Use CCS to debug


why should we add vendor specific IDE instructions here? doesn't west debug just work?

gmarull · 2025-02-03T08:57:17Z

boards/ti/lp_mspm0g3507/lp_mspm0g3507.dts

+	clock-frequency = <DT_FREQ_M(80)>;
+};
+
+&clkmux {
+	clock-source = <&pll>;
+	clock-frequency = <DT_FREQ_M(80)>;


duplicate frequencies here?

gmarull · 2025-02-03T08:57:42Z

boards/ti/lp_mspm0g3507/lp_mspm0g3507_defconfig

+# Enable Clock Control
+CONFIG_CLOCK_CONTROL=y


shouldn't drivers select this?

gmarull · 2025-02-03T08:57:58Z

boards/ti/lp_mspm0g3507/lp_mspm0g3507_defconfig

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CORTEX_M_SYSTICK=y


why is this needed? isn't DT enough?

gmarull · 2025-02-03T08:58:55Z

drivers/clock_control/clock_control_mspm0.c

+#define MSPM0_PLL_ENABLED 1
+#endif
+
+static const DL_SYSCTL_SYSPLLConfig clock_mspm0_cfg_syspll;


static const, uninitialized??

gmarull · 2025-02-03T08:59:37Z

drivers/clock_control/clock_control_mspm0.c

+		rateNotFound = 1;
+		break;
+	}
+	if (rateNotFound == 1) {


please, use booleans..

gmarull · 2025-02-03T09:00:40Z

drivers/clock_control/clock_control_mspm0.c

+static enum clock_control_status clock_mspm0_get_status(const struct device *dev,
+							clock_control_subsys_t sys)
+{
+	return CLOCK_CONTROL_STATUS_UNKNOWN;
+}


gmarull · 2025-02-03T09:01:03Z

drivers/clock_control/clock_control_mspm0.c

+static int clock_mspm0_set_rate(const struct device *dev, clock_control_subsys_t sys,
+				clock_control_subsys_rate_t rate)
+{
+	return -ENOTSUP;
+}
+
+static int clock_mspm0_configure(const struct device *dev, clock_control_subsys_t sys, void *data)
+{
+	return -ENOTSUP;
+}


wrong, pls check API

gmarull · 2025-02-03T09:01:46Z

drivers/gpio/gpio_mspm0.c

+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_utils.h>
+#include <zephyr/irq.h>
+#include <soc.h>


no soc.h please, soc.h is only meant for cmsis

gmarull · 2025-02-03T09:02:08Z

drivers/gpio/gpio_mspm0.c

+	IOMUX_PINCM5,  IOMUX_PINCM6,
+};
+#else
+#throw "series lookup table not supported"


what's "throw"

gmarull · 2025-02-03T12:38:16Z

soc/ti/mspm0/mspm0g1x0x_g3x0x/CMakeLists.txt

+if(CONFIG_SOC_MSPM0G1106)
+	zephyr_compile_definitions(-D__MSPM0G1106__)
+elseif(CONFIG_SOC_MSPM0G1107)
+	zephyr_compile_definitions(-D__MSPM0G1107__)
+elseif(CONFIG_SOC_MSPM0G1506)
+	zephyr_compile_definitions(-D__MSPM0G1506__)
+elseif(CONFIG_SOC_MSPM0G1507)
+	zephyr_compile_definitions(-D__MSPM0G1507__)
+elseif(CONFIG_SOC_MSPM0G3106)
+	zephyr_compile_definitions(-D__MSPM0G3106__)
+elseif(CONFIG_SOC_MSPM0G3107)
+	zephyr_compile_definitions(-D__MSPM0G3107__)
+elseif(CONFIG_SOC_MSPM0G3506)
+	zephyr_compile_definitions(-D__MSPM0G3506__)
+elseif(CONFIG_SOC_MSPM0G3507)
+	zephyr_compile_definitions(-D__MSPM0G3507__)
+endif()


lookd like a HAL requirement, move to glue code.

gmarull · 2025-02-03T12:38:46Z

soc/ti/mspm0/mspm0g1x0x_g3x0x/soc.h

+#define SYSCONFIG_WEAK __attribute__((weak))
+
+#include <ti/devices/msp/msp.h>
+#include <ti/driverlib/driverlib.h>
+#include <ti/driverlib/m0p/dl_core.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Per TRM Section 2.2.7 Peripheral Power Enable Control:
+ *
+ * After setting the ENABLE | KEY bits in the PWREN Register to enable a
+ * peripheral, wait at least 4 ULPCLK clock cycles before accessing the rest of
+ * the peripheral's memory-mapped registers. The 4 cycles allow for the bus
+ * isolation signals at the peripheral's bus interface to update.
+ *
+ * ULPCLK will either be equivalent or half of the main MCLK and CPUCLK,
+ * yielding the delay time of 8 cycles
+ */
+#define POWER_STARTUP_DELAY (8)
+
+#ifdef __cplusplus
+}
+#endif


soc.h is purely for CMSIS glueing, this looks wrong

JFMSP · 2025-03-19T13:13:30Z

@parthitce will continue to drive this PR and open a new PR from his side in order to get the MSPM0 support into the upstream branch.

zephyrbot added area: Clock Control platform: TI SimpleLink Texas Instruments SimpleLink MCU area: Pinctrl area: GPIO area: UART Universal Asynchronous Receiver-Transmitter labels Oct 10, 2024

JFMSP marked this pull request as draft October 10, 2024 18:45

zephyrbot requested review from dcpleung, gmarull, henrikbrixandersen, mnkp, nordic-krch, vaishnavachath and vanti October 10, 2024 18:45

zephyrbot assigned nordic-krch Oct 10, 2024

zephyrbot added manifest manifest-hal_ti DNM This PR should not be merged (Do Not Merge) labels Oct 10, 2024

msp-ti force-pushed the mspm0_upstream branch from 2713ce2 to ec91c9b Compare October 10, 2024 18:52

vaishnavachath previously requested changes Oct 11, 2024

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msp-ti force-pushed the mspm0_upstream branch 2 times, most recently from a2b7ff1 to ca5f253 Compare October 11, 2024 19:50

JFMSP marked this pull request as ready for review October 11, 2024 19:51

zephyrbot added the area: Comparator label Oct 11, 2024

zephyrbot requested a review from bjarki-andreasen October 11, 2024 19:52

vaishnavachath self-requested a review October 11, 2024 20:05

msp-ti force-pushed the mspm0_upstream branch 2 times, most recently from fef4852 to 7c960e4 Compare October 11, 2024 21:16

parthitce reviewed Dec 10, 2024

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parthitce reviewed Dec 10, 2024

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JFMSP force-pushed the mspm0_upstream branch from d4b42c4 to 8d72876 Compare January 16, 2025 23:58

nordicjm requested changes Jan 20, 2025

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JFMSP added 8 commits January 21, 2025 17:34

soc: added initial SOC support for TI MSPM0

24e8378

Added initial SOC support for TI MSPM0 family Signed-off-by: Jackson Farley <[email protected]>

dts: add MSPM0 family to the devicetree

e8f2210

added TI MSPM0 device support to the devicetree Signed-off-by: Jackson Farley <[email protected]>

dts: added pinctrl data for MSPM0

48030a7

added pinctrl data for TI MSPM0 Family Signed-off-by: Jackson Farley <[email protected]>

drivers: added clock control driver for MSPM0

4c0e81d

added clock_control support for TI MSPM0 Family Signed-off-by: Jackson Farley <[email protected]>

drivers: added pinctrl driver for MSPM0

d390b17

added pinctrl driver support for MSPM0 Family Signed-off-by: Jackson Farley <[email protected]>

drivers: added gpio driver for MSPM0 family

cf5480f

Added GPIO driver support for TI MSPM0 family Signed-off-by: Jackson Farley <[email protected]>

drivers: added serial driver for MSPM0

8d0d1fa

added the Serial (uart) driver for MSPM0 family Signed-off-by: Jackson Farley <[email protected]>

boards: added TI LP_MSPM0G3507 board

d0c9952

added Texas Instruments LP_MSPM0G3507 launchpad Signed-off-by: Jackson Farley <[email protected]>

JFMSP force-pushed the mspm0_upstream branch from 8d72876 to d0c9952 Compare January 21, 2025 22:38

JFMSP requested review from nordicjm and parthitce January 29, 2025 21:39

nordicjm requested changes Feb 3, 2025

View reviewed changes

gmarull requested changes Feb 3, 2025

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fabiobaltieri added DNM (manifest) This PR should not be merged (controlled by action-manifest) and removed DNM This PR should not be merged (Do Not Merge) labels Feb 4, 2025

JFMSP closed this Mar 19, 2025

parthitce mentioned this pull request Mar 27, 2025

Texas Instruments (TI) development overview / roadmap #87751

Open

ssekar15 mentioned this pull request Apr 16, 2025

TI MSPM0 SoC series Support #88725

Merged

	Zephyr uses the ``lp_mspm0g3507`` board configuration for building
	Zephyr uses the ``lp_mspm0g3507`` board for building

	default frequency in Hz for clock output
	Default frequency in Hz for clock output

		@@ -0,0 +1,16 @@
		# SPDX-License-Identifier: Apache-2.0

		CONFIG_CORTEX_M_SYSTICK=y

		#include <dt-bindings/pinctrl/mspm0-pinctrl.h>

		&pinctrl {

TI MSPM0 Support #79673

TI MSPM0 Support #79673

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JFMSP commented Oct 10, 2024

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