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TI MSPM0 Support #79673
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TI MSPM0 Support #79673
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| # TI MSPM0 Family | ||||
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| # Copyright (c) 2024, Texas Instruments Inc. | ||||
| # SPDX-License-Identifier: Apache-2.0 | ||||
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| config CLOCK_CONTROL_MSPM0 | ||||
| bool "TI MSPM0 clock" | ||||
| default y | ||||
| depends on SOC_FAMILY_TI_MSPM0 | ||||
| help | ||||
| This option enables the TI MSPM0 Clock Control Enabler | ||||
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| config CLOCK_CONTROL_MSPM0_USE_PLL | ||||
| 
         There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. code consumes it by checking   | 
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| bool "TI MSPM0 Use PLL" | ||||
| default n | ||||
                
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| default n | 
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Implemented spacing correctly
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Not fixed
        
          
              
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| /* | ||
| * Copyright (c) 2024 Texas Instruments | ||
| * | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| */ | ||
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| #include <zephyr/drivers/clock_control.h> | ||
| #include <zephyr/drivers/clock_control/mspm0_clock_control.h> | ||
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| #include <ti/driverlib/driverlib.h> | ||
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| #define ULPCLK_DIV CONCAT(DL_SYSCTL_ULPCLK_DIV_, DT_PROP(DT_NODELABEL(clkmux), uclk_div)) | ||
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| #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) | ||
| #define MSPM0_PLL_ENABLED 1 | ||
| #endif | ||
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| static const DL_SYSCTL_SYSPLLConfig clock_mspm0_cfg_syspll; | ||
| 
         There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. static const, uninitialized??  | 
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| static int clock_mspm0_on(const struct device *dev, clock_control_subsys_t sys) | ||
| { | ||
| return 0; | ||
| } | ||
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| static int clock_mspm0_off(const struct device *dev, clock_control_subsys_t sys) | ||
| { | ||
| return 0; | ||
| } | ||
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| static enum clock_control_status clock_mspm0_get_status(const struct device *dev, | ||
| clock_control_subsys_t sys) | ||
| { | ||
| return CLOCK_CONTROL_STATUS_UNKNOWN; | ||
| } | ||
| 
         
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  There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. redundant  | 
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| static int clock_mspm0_get_rate(const struct device *dev, clock_control_subsys_t sys, | ||
| uint32_t *rate) | ||
| { | ||
| struct mspm0_clockSys *clockSys = (struct mspm0_clockSys *)sys; | ||
| 
         There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. 
 There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Not everyone might be familiar with s(search)/<find>/<replace>/g(global) For those that are not, the reviewer was asking to replace all occurrences of clockSys with clocksys. There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Rule being that Zephyr does not allow camelCase type of syntax (unless it's an external API being used, not belonging to Zephyr like a HAL etc...). So this rule has to be applied everywhere in this PR (saw issues in serial driver as well for instance)         
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| uint8_t rateNotFound = 0; | ||
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| switch (clockSys->bus) { | ||
| case MSPM0_CLOCK_BUS_LFCLK: | ||
| *rate = 32768; | ||
| break; | ||
| case MSPM0_CLOCK_BUS_ULPCLK: | ||
| *rate = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / | ||
| DT_PROP(DT_NODELABEL(clkmux), uclk_div); | ||
| break; | ||
| case MSPM0_CLOCK_BUS_MCLK: | ||
| *rate = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC; | ||
| break; | ||
| case MSPM0_CLOCK_BUS_MFPCLK: | ||
| *rate = 4000000; | ||
| break; | ||
| case MSPM0_CLOCK_BUS_MFCLK: | ||
| case MSPM0_CLOCK_BUS_CANCLK: | ||
| default: | ||
| rateNotFound = 1; | ||
| 
         There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. 
 There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. 
  | 
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| break; | ||
| } | ||
| if (rateNotFound == 1) { | ||
| 
         There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. please, use booleans..  | 
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| return -ENOTSUP; | ||
| } else { | ||
| return 0; | ||
| } | ||
| } | ||
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| static int clock_mspm0_set_rate(const struct device *dev, clock_control_subsys_t sys, | ||
| clock_control_subsys_rate_t rate) | ||
| { | ||
| return -ENOTSUP; | ||
| } | ||
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| static int clock_mspm0_configure(const struct device *dev, clock_control_subsys_t sys, void *data) | ||
| { | ||
| return -ENOTSUP; | ||
| } | ||
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  There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. wrong, pls check API  | 
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| static int clock_mspm0_init(const struct device *dev) | ||
| { | ||
| /* setup clocks based on specific rates */ | ||
| DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE); | ||
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| DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *)&clock_mspm0_cfg_syspll); | ||
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| DL_SYSCTL_setULPCLKDivider(ULPCLK_DIV); | ||
| DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_SYSPLL); | ||
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| return 0; | ||
| } | ||
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| static const struct clock_control_driver_api clock_mspm0_driver_api = { | ||
| .on = clock_mspm0_on, | ||
| .off = clock_mspm0_off, | ||
| .get_status = clock_mspm0_get_status, | ||
| .get_rate = clock_mspm0_get_rate, | ||
| .set_rate = clock_mspm0_set_rate, | ||
| .configure = clock_mspm0_configure}; | ||
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| DEVICE_DT_DEFINE(DT_NODELABEL(clkmux), &clock_mspm0_init, NULL, NULL, NULL, PRE_KERNEL_1, | ||
| 
         There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. More of a general question, when using   | 
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| CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_mspm0_driver_api); | ||
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| #if MSPM0_PLL_ENABLED | ||
| 
         There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Disabling PLL will not boot the device at this point of time. Do we need to conditionally include the below configurations?  | 
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| /* basic checks of the devicetree to follow */ | ||
| #if (DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk2x_div) && \ | ||
| DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk0_div)) | ||
| #error "Only CLK2X or CLK0 can be enabled at a time on the PLL" | ||
| #endif | ||
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| #define GENERATE_PLL_STRUCT() \ | ||
| static const DL_SYSCTL_SYSPLLConfig clock_mspm0_cfg_syspll = { \ | ||
| .inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_32_48_MHZ, \ | ||
| .rDivClk2x = (DT_PROP_OR(DT_NODELABEL(pll), clk2x_div, 1) - 1), \ | ||
| .rDivClk1 = (DT_PROP_OR(DT_NODELABEL(pll), clk1_div, 1) - 1), \ | ||
| .rDivClk0 = (DT_PROP_OR(DT_NODELABEL(pll), clk0_div, 1) - 1), \ | ||
| .qDiv = (DT_PROP(DT_NODELABEL(pll), q_div) - 1), \ | ||
| .pDiv = CONCAT(DL_SYSCTL_SYSPLL_PDIV_, DT_PROP(DT_NODELABEL(pll), p_div)), \ | ||
| .sysPLLMCLK = COND_CODE_1(DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk2x_div), \ | ||
| (DL_SYSCTL_SYSPLL_MCLK_CLK2X), (DL_SYSCTL_SYSPLL_MCLK_CLK0)), \ | ||
| .enableCLK2x = COND_CODE_1(DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk2x_div), \ | ||
| (DL_SYSCTL_SYSPLL_CLK2X_ENABLE), (DL_SYSCTL_SYSPLL_CLK2X_DISABLE)), \ | ||
| .enableCLK1 = COND_CODE_1(DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk1_div), \ | ||
| (DL_SYSCTL_SYSPLL_CLK1_ENABLE), (DL_SYSCTL_SYSPLL_CLK1_DISABLE)), \ | ||
| .enableCLK0 = COND_CODE_1(DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk0_div), \ | ||
| (DL_SYSCTL_SYSPLL_CLK0_ENABLE), (DL_SYSCTL_SYSPLL_CLK0_DISABLE)), \ | ||
| .sysPLLRef = COND_CODE_1(DT_CLOCKS_CELL(DT_NODELABEL(pll), clocks), \ | ||
| (DL_SYSCTL_SYSPLL_REF_HFCLK), (DL_SYSCTL_SYSPLL_REF_SYSOSC)), \ | ||
| }; | ||
| 
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| GENERATE_PLL_STRUCT() | ||
| 
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| #endif /* MSPM0_PLL_ENABLED */ | ||
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| /* SPDX-License-Identifier: Apache-2.0 */ | ||
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| #include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi> | ||
| #include <ti/mspm0g1x0x_g3x0x/mspm0gxxx6.dtsi> | 
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| /* SPDX-License-Identifier: Apache-2.0 */ | ||
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| #include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi> | ||
| #include <ti/mspm0g1x0x_g3x0x/mspm0gxxx7.dtsi> | 
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| #include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x-pinctrl.dtsi> | 
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| /* SPDX-License-Identifier: Apache-2.0 */ | ||
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| #include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi> | ||
| #include <ti/mspm0g1x0x_g3x0x/mspm0gxxx6.dtsi> | 
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| /* SPDX-License-Identifier: Apache-2.0 */ | ||
| 
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| #include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x.dtsi> | ||
| #include <ti/mspm0g1x0x_g3x0x/mspm0gxxx7.dtsi> | 
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| @@ -0,0 +1 @@ | ||
| #include <ti/mspm0g1x0x_g3x0x/mspm0g1x0x_g3x0x-pinctrl.dtsi> | 
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| #include <dt-bindings/pinctrl/mspm0-pinctrl.h> | ||||
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| &pinctrl { | ||||
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| 
         There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Idea is to add all the pin functions? or the ones added in this PR? It's mixed now. Not all is added and also includes pin function for the ones which are not supported in this PR         
       | 
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Not addressed
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nit, spacing and the same across this file
pinmux = <MSP_PINMUX(2, MSPM0_PIN_FUNCTION_3)>;
        
          
              
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bias-pull-up; is missing
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Am not sure why _pull_down/up is missing here. Is it because the pin is High-Drive? Otherwise we don't need to keep a separate suffix for pull_up for all the I2C.
        
          
              
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Not addressed
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TRM calls it as
Clock Module (CKM). May beEnable driver for Clock Module (CKM) found in MSPM0 family of MCUs