TI MSPM0 Support

modules/Kconfig

@@ -24,6 +24,7 @@ source "modules/Kconfig.libmetal"
 source "modules/lvgl/Kconfig"
 source "modules/Kconfig.mcux"
 source "modules/Kconfig.microchip"
+source "modules/Kconfig.mspm0"
 source "modules/Kconfig.nuvoton"
 source "modules/Kconfig.open-amp"
 source "modules/Kconfig.picolibc"

modules/Kconfig.mspm0

@@ -0,0 +1,7 @@
+# MSPM0 SDK configuration
+
+# Copyright (c) 2024 Texas Instruments
+# SPDX-License-Identifier: Apache-2.0
+
+config HAS_MSPM0_SDK
+	bool

soc/ti/mspm0/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "SoC Linker Script")
+
+add_subdirectory(${SOC_SERIES})

soc/ti/mspm0/Kconfig

@@ -0,0 +1,9 @@
+# Texas Instruments MSPM0 Family
+# Copyright (c) 2024 Texas Instruments
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_TI_MSPM0
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_TI_MSPM0

soc/ti/mspm0/Kconfig.defconfig

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 Texas Instruments
+
+if SOC_FAMILY_TI_MSPM0
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_TI_MSPM0

soc/ti/mspm0/Kconfig.soc

@@ -0,0 +1,12 @@
+# Texas Instruments MSPM0 Family
+
+# Copyright (c) 2024 Texas Instruments
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_TI_MSPM0
+	bool
+
+config SOC_FAMILY
+	default "ti_mspm0" if SOC_FAMILY_TI_MSPM0
+
+rsource "*/Kconfig.soc"

soc/ti/mspm0/mspm0g1x0x_g3x0x/CMakeLists.txt

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_MSPM0G1106)
+	zephyr_compile_definitions(-D__MSPM0G1106__)
+elseif(CONFIG_SOC_MSPM0G1107)
+	zephyr_compile_definitions(-D__MSPM0G1107__)
+elseif(CONFIG_SOC_MSPM0G1506)
+	zephyr_compile_definitions(-D__MSPM0G1506__)
+elseif(CONFIG_SOC_MSPM0G1507)
+	zephyr_compile_definitions(-D__MSPM0G1507__)
+elseif(CONFIG_SOC_MSPM0G3106)
+	zephyr_compile_definitions(-D__MSPM0G3106__)
+elseif(CONFIG_SOC_MSPM0G3107)
+	zephyr_compile_definitions(-D__MSPM0G3107__)
+elseif(CONFIG_SOC_MSPM0G3506)
+	zephyr_compile_definitions(-D__MSPM0G3506__)
+elseif(CONFIG_SOC_MSPM0G3507)
+	zephyr_compile_definitions(-D__MSPM0G3507__)
+endif()
+
+zephyr_sources(soc.c)
+zephyr_include_directories(.)

soc/ti/mspm0/mspm0g1x0x_g3x0x/Kconfig

@@ -0,0 +1,14 @@
+# TI MSPM0G1X0X_G3X0X
+
+# Copyright (c) 2024 Texas Instruments
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MSPM0G1X0X_G3X0X
+	select ARM
+	select CPU_CORTEX_M0PLUS
+	select CPU_CORTEX_M_HAS_VTOR
+	select CPU_HAS_ARM_MPU
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select BUILD_OUTPUT_HEX
+	select HAS_MSPM0_SDK
+	select CLOCK_CONTROL

soc/ti/mspm0/mspm0g1x0x_g3x0x/Kconfig.defconfig

@@ -0,0 +1,17 @@
+# TI MSPM0G1X0X_G3X0X
+
+# Copyright (c) 2024 Texas Instruments
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_MSPM0G1X0X_G3X0X
+
+DT_MSPM0_CLKMUX_PATH := $(dt_nodelabel_path,clkmux)
+DT_MSPM0_CLKMUX_CPU_FREQ := $(dt_node_int_prop_int,$(DT_MSPM0_CLKMUX_PATH),clock-frequency)
+
+config NUM_IRQS
+	default 32
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default "$(DT_MSPM0_CLKMUX_CPU_FREQ)" if "$(dt_nodelabel_enabled,clkmux)"
+
+endif # SOC_SERIES_MSPM0G1X0X_G3X0X

soc/ti/mspm0/mspm0g1x0x_g3x0x/Kconfig.soc

@@ -0,0 +1,53 @@
+# Copyright (c) 2024 Texas Instruments
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MSPM0G1X0X_G3X0X
+	bool
+	select SOC_FAMILY_TI_MSPM0
+	help
+	  Enable support for TI MSPM0G1X0X_G3X0X SoCs
+
+config SOC_MSPM0G1106
+	bool
+	select SOC_SERIES_MSPM0G1X0X_G3X0X
+
+config SOC_MSPM0G1107
+	bool
+	select SOC_SERIES_MSPM0G1X0X_G3X0X
+
+config SOC_MSPM0G1506
+	bool
+	select SOC_SERIES_MSPM0G1X0X_G3X0X
+
+config SOC_MSPM0G1507
+	bool
+	select SOC_SERIES_MSPM0G1X0X_G3X0X
+
+config SOC_MSPM0G3106
+	bool
+	select SOC_SERIES_MSPM0G1X0X_G3X0X
+
+config SOC_MSPM0G3107
+	bool
+	select SOC_SERIES_MSPM0G1X0X_G3X0X
+
+config SOC_MSPM0G3506
+	bool
+	select SOC_SERIES_MSPM0G1X0X_G3X0X
+
+config SOC_MSPM0G3507
+	bool
+	select SOC_SERIES_MSPM0G1X0X_G3X0X
+
+config SOC_SERIES
+	default "mspm0g1x0x_g3x0x" if SOC_SERIES_MSPM0G1X0X_G3X0X
+
+config SOC
+	default "mspm0g1106" if SOC_MSPM0G1106
+	default "mspm0g1107" if SOC_MSPM0G1107
+	default "mspm0g1506" if SOC_MSPM0G1506
+	default "mspm0g1507" if SOC_MSPM0G1507
+	default "mspm0g3106" if SOC_MSPM0G3106
+	default "mspm0g3107" if SOC_MSPM0G3107
+	default "mspm0g3506" if SOC_MSPM0G3506
+	default "mspm0g3507" if SOC_MSPM0G3507

soc/ti/mspm0/mspm0g1x0x_g3x0x/pinctrl_soc.h

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) (2024) Texas Instruments
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef SOC_TI_MSPM0_M0G1X0X_G3X0X_PINCTRL_SOC_H_
+#define SOC_TI_MSPM0_M0G1X0X_G3X0X_PINCTRL_SOC_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/types.h>
+#include <zephyr/dt-bindings/pinctrl/mspm0-pinctrl.h>
+
+#define MSP_GPIO_RESISTOR_PULL_DOWN (16)
+#define MSP_GPIO_RESISTOR_PULL_UP   (17)
+#define MSP_GPIO_INPUT_ENABLE       (18)
+#define MSP_GPIO_HYSTERESIS_ENABLED (19)
+#define MSP_GPIO_OPEN_DRAIN_OUTPUT  (25)
+#define MSP_GPIO_INVERSION_ENABLED  (26)
+
+#define MSP_GPIO_HIGH_DRIVE (20)
+
+#define MSP_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux)
+
+#define MSP_PIN_CONTROL_IOMUX_INIT(node_id)                                                        \
+	((DT_PROP(node_id, bias_pull_up) << MSP_GPIO_RESISTOR_PULL_UP) |                           \
+	 (DT_PROP(node_id, bias_pull_down) << MSP_GPIO_RESISTOR_PULL_DOWN) |                       \
+	 (DT_PROP(node_id, drive_open_drain) << MSP_GPIO_OPEN_DRAIN_OUTPUT) |                      \
+	 (DT_PROP(node_id, ti_hysteresis) << MSP_GPIO_HYSTERESIS_ENABLED) |                        \
+	 (DT_PROP(node_id, ti_invert) << MSP_GPIO_INVERSION_ENABLED) |                             \
+	 (DT_PROP(node_id, input_enable) << MSP_GPIO_INPUT_ENABLE))
+
+typedef struct pinctrl_soc_pin {
+	/* PINCM register index and pin function */
+	uint32_t pinmux;
+	/* IOMUX Pin Control Management (direction, inversion, pullups) */
+	uint32_t iomux;
+} pinctrl_soc_pin_t;
+
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)                                               \
+	{.pinmux = MSP_PINMUX_INIT(DT_PROP_BY_IDX(node_id, prop, idx)),                            \
+	 .iomux = MSP_PIN_CONTROL_IOMUX_INIT(DT_PROP_BY_IDX(node_id, prop, idx))},
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
+	{                                                                                          \
+		DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)                      \
+	}
+
+#endif /* SOC_TI_MSPM0_M0G1X0X_G3X0X_PINCTRL_SOC_H_ */

soc/ti/mspm0/mspm0g1x0x_g3x0x/soc.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 Texas Instruments
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/init.h>
+#include <soc.h>
+
+void soc_early_init_hook(void)
+{
+	/* Reset and enable GPIO banks */
+	DL_GPIO_reset(GPIOA);
+	DL_GPIO_reset(GPIOB);
+
+	DL_GPIO_enablePower(GPIOA);
+	DL_GPIO_enablePower(GPIOB);
+
+	/* Allow delay time to settle */
+	delay_cycles(POWER_STARTUP_DELAY);
+
+	/* Low Power Mode is configured to be SLEEP0 */
+	DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
+}

soc/ti/mspm0/mspm0g1x0x_g3x0x/soc.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024 Texas Instruments
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef SOC_TI_MSPM0_SOC_H_
+#define SOC_TI_MSPM0_SOC_H_
+
+#define SYSCONFIG_WEAK __attribute__((weak))
+
+#include <ti/devices/msp/msp.h>
+#include <ti/driverlib/driverlib.h>
+#include <ti/driverlib/m0p/dl_core.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Per TRM Section 2.2.7 Peripheral Power Enable Control:
+ *
+ * After setting the ENABLE | KEY bits in the PWREN Register to enable a
+ * peripheral, wait at least 4 ULPCLK clock cycles before accessing the rest of
+ * the peripheral's memory-mapped registers. The 4 cycles allow for the bus
+ * isolation signals at the peripheral's bus interface to update.
+ *
+ * ULPCLK will either be equivalent or half of the main MCLK and CPUCLK,
+ * yielding the delay time of 8 cycles
+ */
+#define POWER_STARTUP_DELAY (8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SOC_TI_MSPM0_SOC_H_ */

soc/ti/mspm0/soc.yml

@@ -0,0 +1,13 @@
+family:
+- name: ti_mspm0
+  series:
+  - name: mspm0g1x0x_g3x0x
+    socs:
+    - name: mspm0g1106
+    - name: mspm0g1107
+    - name: mspm0g1506
+    - name: mspm0g1507
+    - name: mspm0g3106
+    - name: mspm0g3107
+    - name: mspm0g3506
+    - name: mspm0g3507