i.MX RT700 DSP support

boards/nxp/mimxrt700_evk/Kconfig.mimxrt700_evk

@@ -1,7 +1,9 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_MIMXRT700_EVK
 	select SOC_MIMXRT798S_CM33_CPU0 if BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0
 	select SOC_MIMXRT798S_CM33_CPU1 if BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1
+	select SOC_MIMXRT798S_HIFI4 if BOARD_MIMXRT700_EVK_MIMXRT798S_HIFI4
+	select SOC_MIMXRT798S_HIFI1 if BOARD_MIMXRT700_EVK_MIMXRT798S_HIFI1
 	select SOC_PART_NUMBER_MIMXRT798SGFOA

boards/nxp/mimxrt700_evk/board.cmake

@@ -13,8 +13,6 @@ elseif(CONFIG_SOC_MIMXRT798S_CM33_CPU1)
   board_runner_args(jlink "--device=MIMXRT798S_M33_1")
   board_runner_args(linkserver  "--device=MIMXRT798S:MIMXRT700-EVK")
   board_runner_args(linkserver  "--core=cm33_core1")
-else()
-  message(FATAL_ERROR "Requested core is not supported")
 endif()
 
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/nxp/mimxrt700_evk/doc/index.rst

@@ -3,26 +3,31 @@
 Overview
 ********
 
-The new i.MX RT700 CPU architecture is composed of a high-performance main compute subsystem,
+The new i.MX RT700 CPU architecture is composed of a high-performance main-compute subsystem,
 a secondary “always-on” sense-compute subsystem and specialized coprocessors.
 
-The main compute subsystem uses a 325 MHz capable Arm® Cortex®-M33 (CM33).
-Similar to the i.MX RT600 crossover MCU, the i.MX RT700 includes a Cadence Tensilica® HiFi 4 DSP.
-The HiFi 4 is a high performance DSP core based upon a Very Long Instruction Word (VLIW) architecture,
+The main-compute subsystem has a primary Arm® Cortex®-M33 running at 325 MHz, with an integrated
+Cadence® Tensilica® HiFi 4 DSP for more demanding DSP and audio processing tasks.
+The sense-compute subsystem has a second Arm® Cortex®-M33 and an integrated Cadence® Tensilica®
+HiFi 1 DSP. This removes the need for an external sensor hub, reducing system design complexity,
+footprint and BOM costs.
+
+The HiFi4 is a high performance DSP core based upon a Very Long Instruction Word (VLIW) architecture,
 which is capable of processing up to eight 32x16 MACs per instruction cycle. It can be used for offloading
 high-performance numerical tasks such as audio and image processing and supports both fixed-point and
 floating-point operations.
 
+The i.MX RT700 also features NXP’s eIQ Neutron NPU, enabled with the eIQ machine learning software
+development environment.
+
 Hardware
 ********
 
 - Main Compute Subsystem:
-
    - Arm Cortex-M33 up to 325 MHz
    - HiFi 4 DSP up to 325 MHz
    - eIQ Neutron NPU up to 325 MHz
 - Sense Compute Subsystem:
-
    - Arm Cortex-M33 up to 250 MHz
    - HiFi 1 DSP up to 250 MHz
 - 7.5 MB on-chip SRAM
@@ -49,9 +54,9 @@ Supported Features
 ==================
 
 NXP considers the MIMXRT700-EVK as a superset board for the i.MX RT7xx
-family of MCUs.  This board is a focus for NXP's Full Platform Support for
-Zephyr, to better enable the entire RT7xx family.  NXP prioritizes enabling
-this board with new support for Zephyr features.  The ``mimxrt700_evk/mimxrt798s
+family of MCUs. This board is a focus for NXP's Full Platform Support for
+Zephyr, to better enable the entire RT7xx family. NXP prioritizes enabling
+this board with new support for Zephyr features. The ``mimxrt700_evk/mimxrt798s
 /cm33_cpu0`` and ``mimxrt700_evk/mimxrt798s/cm33_cpu1`` board targets support
 the hardware features below.
 
@@ -131,6 +136,34 @@ System Clock
 The MIMXRT700 EVK is configured to use the Systick
 as a source for the system clock.
 
+HiFi1 DSP Core
+==================
+
+One can build a Zephyr application for the i.MX RT700 HiFi 1  DSP core by targeting the HiFi 1
+SOC. Xtensa toolchain supporting RT700 DSP cores is included in Zephyr SDK.
+
+To build the hello_world sample for the i.MX RT700 HiFi 1 DSP core:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: mimxrt700_evk/mimxrt798s/hifi1
+   :goals: build
+
+HiFi4 DSP Core
+==================
+
+One can build a Zephyr application for the i.MX RT700 HiFi 4  DSP core by targeting the HiFi 4
+SOC. Xtensa toolchain supporting RT700 DSP cores is included in Zephyr SDK.
+
+To build the hello_world sample for the i.MX RT700 HiFi 4 DSP core:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: mimxrt700_evk/mimxrt798s/hifi4
+   :goals: build
+
 Programming and Debugging
 *************************
 

boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi1.dts

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_imxrt700_hifi1.dtsi>
+
+/ {
+	model = "NXP MIMXRT700-EVK HiFi1 DSP";
+	compatible = "nxp,mimxrt798s";
+
+	chosen {
+		zephyr,sram = &dtcm;
+	};
+};

boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi1.yaml

@@ -0,0 +1,18 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt700_evk/mimxrt798s/hifi1
+name: NXP MIMXRT700-EVK HiFi1
+type: mcu
+arch: xtensa
+toolchain:
+  - xcc
+  - xt-clang
+  - zephyr
+testing:
+  only_tags:
+    - kernel
+vendor: nxp

boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_imxrt700_hifi4.dtsi>
+
+/ {
+	model = "NXP MIMXRT700-EVK HiFi4 DSP";
+	compatible = "nxp,mimxrt798s";
+
+	chosen {
+		zephyr,sram = &dtcm;
+	};
+};

boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.yaml

@@ -0,0 +1,18 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt700_evk/mimxrt798s/hifi4
+name: NXP MIMXRT700-EVK HiFi4
+type: mcu
+arch: xtensa
+toolchain:
+  - xcc
+  - xt-clang
+  - zephyr
+testing:
+  only_tags:
+    - kernel
+vendor: nxp

dts/xtensa/nxp/nxp_imxrt700_hifi1.dtsi

@@ -0,0 +1,41 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <xtensa/xtensa.dtsi>
+#include <freq.h>
+#include <mem.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "cdns,tensilica-xtensa-lx7";
+			clock-frequency = <DT_FREQ_M(250)>;
+			reg = <0>;
+		};
+	};
+
+	itcm0: memory@580000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x580000 DT_SIZE_K(32)>;
+	};
+
+	itcm1: memory@680000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x680000 DT_SIZE_K(512)>;
+	};
+
+	dtcm: memory@20700000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x20700000 DT_SIZE_K(512)>;
+	};
+};

dts/xtensa/nxp/nxp_imxrt700_hifi4.dtsi

@@ -0,0 +1,35 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <xtensa/xtensa.dtsi>
+#include <freq.h>
+#include <mem.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "cdns,tensilica-xtensa-lx7";
+			clock-frequency = <DT_FREQ_M(325)>;
+			reg = <0>;
+		};
+	};
+
+	itcm: memory@24020000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x24020000 DT_SIZE_K(64)>;
+	};
+
+	dtcm: memory@24000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x24000000 DT_SIZE_K(64)>;
+	};
+};

soc/nxp/imxrt/imxrt7xx/CMakeLists.txt

@@ -1,9 +1,13 @@
 #
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
 
 if(CONFIG_SOC_MIMXRT798S_CM33_CPU0 OR CONFIG_SOC_MIMXRT798S_CM33_CPU1)
   add_subdirectory(cm33)
+elseif(CONFIG_SOC_MIMXRT798S_HIFI4)
+  add_subdirectory(hifi4)
+elseif(CONFIG_SOC_MIMXRT798S_HIFI1)
+  add_subdirectory(hifi1)
 endif()

soc/nxp/imxrt/imxrt7xx/Kconfig

@@ -1,4 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_MIMXRT798S_CM33_CPU0
@@ -38,6 +38,26 @@ config SOC_MIMXRT798S_CM33_CPU1
 	select HAS_MCUX_SYSCON
 	select HAS_MCUX_FLEXCOMM
 
+config SOC_MIMXRT798S_HIFI4
+	select XTENSA
+	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
+	select XTENSA_RESET_VECTOR
+	select XTENSA_USE_CORE_CRT1
+	select XTENSA_GEN_HANDLERS
+	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
+	select GEN_ISR_TABLES
+	select HAS_MCUX
+
+config SOC_MIMXRT798S_HIFI1
+	select XTENSA
+	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
+	select XTENSA_RESET_VECTOR
+	select XTENSA_USE_CORE_CRT1
+	select XTENSA_GEN_HANDLERS
+	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
+	select GEN_ISR_TABLES
+	select HAS_MCUX
+
 if SOC_SERIES_IMXRT7XX
 
 if NXP_IMXRT_BOOT_HEADER
@@ -54,5 +74,7 @@ config GLIKEY_MCUX_GLIKEY
 config MCUX_CORE_SUFFIX
 	default "_cm33_core0" if SOC_MIMXRT798S_CM33_CPU0
 	default "_cm33_core1" if SOC_MIMXRT798S_CM33_CPU1
+	default "_hifi4" if SOC_MIMXRT798S_HIFI4
+	default "_hifi1" if SOC_MIMXRT798S_HIFI1
 
 endif # SOC_SERIES_IMXRT7XX

soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig

@@ -33,3 +33,47 @@ endif # SOC_MIMXRT798S_CM33_CPU1
 config MFD
 	default y
 	depends on DT_HAS_NXP_LP_FLEXCOMM_ENABLED
+
+if SOC_MIMXRT798S_HIFI4
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config XTENSA_TIMER
+	default y
+
+config XTENSA_CCOUNT_HZ
+	default SYS_CLOCK_HW_CYCLES_PER_SEC
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1000
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+config NXP_IMXRT_BOOT_HEADER
+	default n
+
+endif # SOC_MIMXRT798S_HIFI4
+
+if SOC_MIMXRT798S_HIFI1
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config XTENSA_TIMER
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+config NXP_IMXRT_BOOT_HEADER
+	default n
+
+config XTENSA_CCOUNT_HZ
+	default SYS_CLOCK_HW_CYCLES_PER_SEC
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1000
+
+endif # SOC_MIMXRT798S_HIFI1