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30 changes: 30 additions & 0 deletions drivers/fpga/fpga_ice40.c
Original file line number Diff line number Diff line change
Expand Up @@ -207,6 +207,26 @@ static int fpga_ice40_load_gpio(const struct device *dev, uint32_t *image_ptr, u
struct fpga_ice40_data *data = dev->data;
const struct fpga_ice40_config *config = dev->config;

if (!device_is_ready(config->clk.port)) {
LOG_ERR("%s: GPIO for clk is not ready", dev->name);
return -ENODEV;
}

if (!device_is_ready(config->pico.port)) {
LOG_ERR("%s: GPIO for pico is not ready", dev->name);
return -ENODEV;
}

if (config->set == NULL) {
LOG_ERR("%s: set register was not specified", dev->name);
return -EFAULT;
}

if (config->clear == NULL) {
LOG_ERR("%s: clear register was not specified", dev->name);
return -EFAULT;
}

Comment on lines +220 to +229
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It might be possible to move this check at build-time by removing the _OR from here:

#define FPGA_ICE40_GPIO_PINS(inst, name) (volatile gpio_port_pins_t *)DT_INST_PROP_OR(inst, name, 0)

But it is still allowed to be empty for SPI, so it could be some build assert checking FPGA_ICE40_LOAD_MODE(inst) eventually.

A run-time check is good too!

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+1 for build-time checks.

/* prepare masks */
cs = BIT(config->bus.config.cs.gpio.pin);
clk = BIT(config->clk.pin);
Expand Down Expand Up @@ -502,6 +522,16 @@ static int fpga_ice40_init(const struct device *dev)
int ret;
const struct fpga_ice40_config *config = dev->config;

if (!device_is_ready(config->creset.port)) {
LOG_ERR("%s: GPIO for creset is not ready", dev->name);
return -ENODEV;
}

if (!device_is_ready(config->cdone.port)) {
LOG_ERR("%s: GPIO for cdone is not ready", dev->name);
return -ENODEV;
}

ret = gpio_pin_configure_dt(&config->creset, GPIO_OUTPUT_HIGH);
if (ret < 0) {
LOG_ERR("failed to configure CRESET: %d", ret);
Expand Down
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