tests: drivers: clock control stm32 adc device clock setting #81089
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platform: STM32
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Let's be more explicit on the clock in use
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nucleo_g071rb DTS gives SYSCLK as clock source for the ADC1
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One of these test cases doesn't have a matching test configuration and will end as dead code.
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adding #if defined(STM32_SRC_SYSCLK) and #if defined(STM32_SRC_HSI)
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...trol/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration_adc.c
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Tests the ADC clock domain on the stm32g0 serie Possible ADC clock sources are SYStem clock (default) or PLL_P. No clock source HSI for the ADC tested here. Signed-off-by: Francois Ramu <[email protected]>
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ping @nordic-krch |
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Tests the ADC clock domain on the stm32g0 serie
Possible ADC clock sources are system clock or PLL_P or HSI
Running the tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices on the nucleo_g071rb
with boards/g0_i2c1_sysclk_lptim1_lsi.overlay, can detect the ADC clock sources :