NXP S32Z: add support to execute code from code RAM #81112
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Use Zephyr cache API to initialize cache as done for various platforms. Enabling CACHE_MANAGEMENT by default Signed-off-by: Dat Nguyen Duy <[email protected]>
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ithinuel,
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nashif and
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manuargue
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On Arm Cortex R52, cache segregation policy controls the number of L1 I/D cache ways that are allocated to Flash and AXIM interface. Adding Kconfig options for configuring it. Writing to IMP_CSCTRL is only permitted before the caches have been enabled, following a system reset. Signed-off-by: Dat Nguyen Duy <[email protected]>
Add devicetree node for code RAM, code RAM can be accessed over AIXM bus or AXIF bus. Code access via AXIF interface provides the best optimal performance Signed-off-by: Dat Nguyen Duy <[email protected]>
- Trace32 runner: no need to configure TE bit in CFG_CORE register in the cmm start-up script, it can be configured at Zephyr start-up code when required (via SCTRL register) - MPU static regions also needs to be updated for XIP and non-XIP Signed-off-by: Dat Nguyen Duy <[email protected]>
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manuargue
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SoC changes LGTM, I'll let others review the Arm changes and approve after
ithinuel
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Nov 25, 2024
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| zephyr,sram = &sram1; | ||
| zephyr,console = &uart0; |
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Is dropping the console here intended ?
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Hi, yes the change is intended because the console is already chosen in https://github.com/zephyrproject-rtos/zephyr/blob/main/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_B.overlay (for revB) and https://github.com/zephyrproject-rtos/zephyr/blob/main/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.overlay (for revD)
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if the change is unrelated to this pr then consider doing it in a separate pr
ithinuel
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Nov 26, 2024
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Changes to the arch/arm parts look good to me.
The rest seems fine too.
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Nov 26, 2024
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This PR adds support to execute code from code RAM through AXIF (a read-only bus interface)
Fixes #60217