Skip to content

drivers: dma: intel-adsp-hda: optimize L1 exit handling in ISR #81152

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
aescolar merged 2 commits into from
Nov 21, 2024
Merged

drivers: dma: intel-adsp-hda: optimize L1 exit handling in ISR #81152

Changes from 1 commit
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
9131603
drivers: dma: intel-adsp-hda: optimize L1 exit handling in ISR
kv2019i Nov 8, 2024
a2f1f78
drivers: dma: intel-adsp-hda: coding style fix
kv2019i Nov 18, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 6 additions & 3 deletions drivers/dma/dma_intel_adsp_hda.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -459,6 +459,7 @@ void intel_adsp_hda_dma_isr(void)
bool triggered_interrupts = false;
int i, j;
int expected_interrupts = 0;
atomic_val_t enabled_chs;
const struct device *host_dev[] = {
#if CONFIG_DMA_INTEL_ADSP_HDA_HOST_OUT
DT_FOREACH_STATUS_OKAY(intel_adsp_hda_host_out, DEVICE_DT_GET_AND_COMMA)
Expand All @@ -479,10 +480,12 @@ void intel_adsp_hda_dma_isr(void)
for (i = 0; i < ARRAY_SIZE(host_dev); i++) {
dma_ctx = (struct dma_context *)host_dev[i]->data;
cfg = host_dev[i]->config;

for (j = 0; j < dma_ctx->dma_channels; j++) {
if (!atomic_test_bit(dma_ctx->atomic, j))
enabled_chs = atomic_get(dma_ctx->atomic);
Copy link
Contributor

@lyakh lyakh Nov 19, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

this suggests that the .atomic field cannot change while we're in the ISR? Also not by a different core?

Copy link
Contributor Author

@kv2019i kv2019i Nov 21, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@lyakh It can change, but it's harmless for this loop as either we do one unnecessary check (for a channel that is already disabled by another core), or we have an additional ISR if it's enabled concurrently.

Copy link
Contributor

@lyakh lyakh Nov 22, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@kv2019i ok, sounds good, thanks for explaining! If we ever end up changing this file again, maybe would be good to add this as a comment there

for (j = 0; enabled_chs && j < dma_ctx->dma_channels; j++) {
if (!(enabled_chs & BIT(j))) {
continue;
}
enabled_chs &= ~(BIT(j));
Copy link
Contributor

@lyakh lyakh Nov 19, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

BIT() is properly defined, no need for additional parentheses

Copy link
Contributor Author

@kv2019i kv2019i Nov 21, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Ok this got merged already, I can fix if we have other changes to do in a follow-up.


if (!intel_adsp_hda_is_buffer_interrupt_enabled(cfg->base,
cfg->regblock_size, j))
Expand Down