Fix SPI load mode of the FPGA iCE40 #81212
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I am fairly confident that the CI failure is not caused by this PR: |
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The datasheet of the iCE40 specifies that there should be a leading and trailing clocks phase during its configuration with SPI. Due to the limitations of the SPI interface, and probably also due to a lock of support for such a feature for instance in the STM32 SPI peripheral, this is achieved with additional SPI transfers before and after the actual image. Unfortunately, this by default also affects the slave select GPIO, which has to stay high during these phases. This fixes this behaviour via not passing the slave select GPIO to the SPI driver and manipulating this GPIO manually. Signed-off-by: Benedikt Schmidt <[email protected]>
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Replaced memset for CS gpio with a cs.gpio.port = NULL, according to the comment of @tbursztyka. |
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The configuration procedure for the FPGA iCE40 requires a leading and trailing clocks phase, which is currently implemented through additional SPI transfers before and after the actual FPGA image. Unfortunately, this also modifies the CS line, which therefore leads to a waveform which doesn't adhere to the specification.
This PR changes this behavior to ensure compliance with the iCE40 datasheet during the configuration.
Leading clocks phase before:
Leading clocks phase after:
