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This makes the two load modes for the iCE40 optional and represents therefore a workaround for #77983.

@benediktibk benediktibk force-pushed the add/ice40_optional_load_modes branch from 71b67b7 to 0cd5610 Compare November 4, 2024 14:28
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based upon #80846

@benediktibk benediktibk force-pushed the add/ice40_optional_load_modes branch 2 times, most recently from f8a5714 to 9bb2f9a Compare November 11, 2024 09:04
@benediktibk benediktibk force-pushed the add/ice40_optional_load_modes branch from 9bb2f9a to aa5e589 Compare November 18, 2024 06:15
@benediktibk benediktibk marked this pull request as ready for review November 18, 2024 06:34
@zephyrbot zephyrbot added the area: FPGA Field-Programmable Gate Array (FPGA) label Nov 18, 2024
@benediktibk benediktibk requested a review from josuah November 18, 2024 06:36
@benediktibk benediktibk force-pushed the add/ice40_optional_load_modes branch 4 times, most recently from 6b81733 to c10a486 Compare November 18, 2024 10:06
josuah
josuah previously approved these changes Nov 18, 2024
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I really like the direction it is taking, but wonder if it would be interesting to split this in 2 drivers in the same file, using two different compatibles:

#define ICE40_FIELDS_COMMON(inst) \
		.creset = GPIO_DT_SPEC_INST_GET(inst, creset_gpios),               \
		.cdone = GPIO_DT_SPEC_INST_GET(inst, cdone_gpios),                 \
		.mhz_delay_count = FPGA_ICE40_MHZ_DELAY_COUNT(inst),               \
		.config_delay_us = FPGA_ICE40_CONFIG_DELAY_US(inst),               \
		.creset_delay_us = FPGA_ICE40_CRESET_DELAY_US(inst),               \
		.leading_clocks = FPGA_ICE40_LEADING_CLOCKS(inst),                 \
		.trailing_clocks = FPGA_ICE40_TRAILING_CLOCKS(inst),               \


#define ICE40_DEFINE_SPI(inst) \
	static struct fpga_ice40_data fpga_ice40_data_##inst;                      \
                                                                                   \
	static const struct fpga_ice40_config fpga_ice40_config_##inst = {         \
		ICE40_FIELDS_COMMON(inst)                                          \
		.bus = SPI_DT_SPEC_INST_GET(inst, SPI_WORD_SET(8) | SPI_TRANSFER_MSB, 0),\
		.load = fpga_ice40_load_spi};                                      \
                                                                                   \
	DEVICE_DT_INST_DEFINE(inst, fpga_ice40_init, NULL, &fpga_ice40_data_##inst,\
			      &fpga_ice40_config_##inst, POST_KERNEL, CONFIG_FPGA_INIT_PRIORITY,\
			      &fpga_ice40_api);

#define ICE40_DEFINE_GPIO(inst) \
	FPGA_ICE40_PINCTRL_DEFINE(inst);                                           \
                                                                                   \
	static struct fpga_ice40_data fpga_ice40_data_##inst;                      \
                                                                                   \
	static const struct fpga_ice40_config fpga_ice40_config_##inst = {         \
		ICE40_FIELDS_COMMON(inst)                                          \
		.clk = GPIO_DT_SPEC_INST_GET_OR(inst, clk_gpios, {0}),             \
		.pico = GPIO_DT_SPEC_INST_GET_OR(inst, pico_gpios, {0}),           \
		.set = FPGA_ICE40_GPIO_PINS(inst, gpios_set_reg),                  \
		.clear = FPGA_ICE40_GPIO_PINS(inst, gpios_clear_reg),              \
		.load = fpga_ice40_load_gpio,                                      \
		FPGA_ICE40_PINCTRL_CONFIG(inst)};                                  \
                                                                                   \
	DEVICE_DT_INST_DEFINE(inst, fpga_ice40_init, NULL, &fpga_ice40_data_##inst,\
			      &fpga_ice40_config_##inst, POST_KERNEL, CONFIG_FPGA_INIT_PRIORITY,\
			      &fpga_ice40_api);


#define DT_DRV_COMPAT lattice_ice40_spi
DT_INST_FOREACH_STATUS_OKAY(ICE40_DEFINE)
#undef DT_DRV_COMPAT

#define DT_DRV_COMPAT lattice_ice40_gpio
DT_INST_FOREACH_STATUS_OKAY(ICE40_DEFINE)
#undef DT_DRV_COMPAT

That is a breaking change, though, and the change you introduced are not: +1 with/without splitting the bindings.

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I really like the direction it is taking, but wonder if it would be interesting to split this in 2 drivers in the same file, using two different compatibles:

Interesting idea, and the breaking change should not be a big issue as the driver is still experimental. @cfriedt Preferences from your side?

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cfriedt commented Nov 18, 2024

Yeah, until we have better support for deinitializing SPI controllers, I guess anything is better than not having multi-instance.

Let's try two DT compats - why not?

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Yeah, until we have better support for deinitializing SPI controllers, I guess anything is better than not having multi-instance.

Let's try two DT compats - why not?

Okay, I will do so. But I'm gonna wait until #81212 is merged to avoid a conflict.

@benediktibk benediktibk marked this pull request as draft November 19, 2024 07:41
@benediktibk benediktibk force-pushed the add/ice40_optional_load_modes branch 4 times, most recently from 8665ce3 to f99582e Compare November 26, 2024 12:09
@benediktibk benediktibk marked this pull request as ready for review November 26, 2024 12:13
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I've separated the drivers into a SPI and GPIO bitbang implementation, with two different compatibles. I've kept the original binding as it is to avoid necessary changes downstream.

@benediktibk benediktibk force-pushed the add/ice40_optional_load_modes branch from f99582e to 9e06e2b Compare November 26, 2024 12:51
@zephyrbot zephyrbot added the Release Notes To be mentioned in the release notes label Nov 26, 2024
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Added a bullet point in the release notes for the change in the binding.

@benediktibk benediktibk force-pushed the add/ice40_optional_load_modes branch from 9e06e2b to 747ecad Compare November 26, 2024 12:57
@benediktibk benediktibk requested a review from josuah November 26, 2024 15:24
josuah
josuah previously approved these changes Nov 26, 2024
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Thank you very much for this effort. I could as well be doing it since I suggested the changes...

The situation seems very clear now. Alot of #ifdef and BUILD_ASSERT() removed.

cfriedt
cfriedt previously approved these changes Nov 27, 2024
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@cfriedt Btw, I've removed the experimental flag from the SPI-based driver, as I think the experimental state at least for this driver should be gone with this state.

@benediktibk benediktibk dismissed stale reviews from cfriedt and josuah via 27a5aa7 November 27, 2024 07:01
@benediktibk benediktibk force-pushed the add/ice40_optional_load_modes branch 2 times, most recently from 27a5aa7 to ac5ee9d Compare November 27, 2024 08:04
Separate the current driver for the FPGA iCE40 into two different ones.
One implements only the SPI load mode, the other one only the GPIO
bitbang mode.

Signed-off-by: Benedikt Schmidt <[email protected]>
@benediktibk benediktibk force-pushed the add/ice40_optional_load_modes branch from ac5ee9d to 8b212b8 Compare November 27, 2024 09:40
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The compliance check error was interesting:

/bin/sh: 1: gitlint: not found

Did a rebase onto main to trigger the CI.

@benediktibk benediktibk requested a review from cfriedt November 27, 2024 19:25
@fabiobaltieri fabiobaltieri merged commit 760210f into zephyrproject-rtos:main Nov 28, 2024
24 checks passed
@benediktibk benediktibk deleted the add/ice40_optional_load_modes branch November 28, 2024 20:01
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5 participants