arch: riscv: smp: allow custom IPI implementation, add PLIC-based IPI

arch/arc/core/smp.c

@@ -16,6 +16,7 @@
 #include <ipi.h>
 #include <zephyr/init.h>
 #include <zephyr/irq.h>
+#include <zephyr/platform/hooks.h>
 #include <arc_irq_offload.h>
 
 volatile struct {
@@ -115,6 +116,11 @@ void arch_secondary_cpu_init(int cpu_num)
 			   DT_IRQ(DT_NODELABEL(ici), priority), 0);
 	irq_enable(DT_IRQN(DT_NODELABEL(ici)));
 #endif
+
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
+
 	/* call the function set by arch_cpu_start */
 	fn = arc_cpu_init[cpu_num].fn;
 

arch/arc/include/kernel_arch_func.h

@@ -26,13 +26,19 @@
 
 #include <v2/irq.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 static ALWAYS_INLINE void arch_kernel_init(void)
 {
 	z_irq_setup();
+
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 

arch/arm/core/cortex_a_r/smp.c

@@ -12,6 +12,7 @@
 #include "zephyr/cache.h"
 #include "zephyr/kernel/thread_stack.h"
 #include "zephyr/toolchain/gcc.h"
+#include <zephyr/platform/hooks.h>
 
 #define INV_MPID	UINT32_MAX
 
@@ -198,6 +199,10 @@ void arch_secondary_cpu_init(void)
 	 */
 #endif
 
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
+
 	fn = arm_cpu_boot_params.fn;
 	arg = arm_cpu_boot_params.arg;
 	barrier_dsync_fence_full();

arch/arm/include/cortex_a_r/kernel_arch_func.h

@@ -20,6 +20,8 @@
 #ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_KERNEL_ARCH_FUNC_H_
 #define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_KERNEL_ARCH_FUNC_H_
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -28,6 +30,9 @@ extern "C" {
 
 static ALWAYS_INLINE void arch_kernel_init(void)
 {
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 #ifndef CONFIG_USE_SWITCH

arch/arm/include/cortex_m/kernel_arch_func.h

@@ -20,6 +20,8 @@
 #ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_KERNEL_ARCH_FUNC_H_
 #define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_KERNEL_ARCH_FUNC_H_
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -53,6 +55,10 @@ static ALWAYS_INLINE void arch_kernel_init(void)
 	 */
 	z_arm_configure_static_mpu_regions();
 #endif /* CONFIG_ARM_MPU */
+
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 static ALWAYS_INLINE void

arch/arm64/core/smp.c

@@ -23,6 +23,7 @@
 #include <zephyr/drivers/interrupt_controller/gic.h>
 #include <zephyr/drivers/pm_cpu_ops.h>
 #include <zephyr/arch/arch_interface.h>
+#include <zephyr/platform/hooks.h>
 #include <zephyr/sys/barrier.h>
 #include <zephyr/irq.h>
 #include "boot.h"
@@ -163,6 +164,10 @@ void arch_secondary_cpu_init(int cpu_num)
 #endif
 #endif
 
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
+
 	fn = arm64_cpu_boot_params.fn;
 	arg = arm64_cpu_boot_params.arg;
 	barrier_dsync_fence_full();

arch/arm64/include/kernel_arch_func.h

@@ -22,6 +22,8 @@
 
 #include <kernel_arch_data.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -35,6 +37,10 @@ static ALWAYS_INLINE void arch_kernel_init(void)
 #ifdef CONFIG_XEN
 	xen_enlighten_init();
 #endif
+
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 static inline void arch_switch(void *switch_to, void **switched_from)

arch/mips/include/kernel_arch_func.h

@@ -19,13 +19,18 @@
 
 #include <kernel_arch_data.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #ifndef _ASMLANGUAGE
 static ALWAYS_INLINE void arch_kernel_init(void)
 {
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 static ALWAYS_INLINE void

arch/nios2/include/kernel_arch_func.h

@@ -22,6 +22,8 @@
 
 #include <kernel_arch_data.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -30,6 +32,9 @@ extern "C" {
 
 static ALWAYS_INLINE void arch_kernel_init(void)
 {
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 static ALWAYS_INLINE void

arch/posix/include/kernel_arch_func.h

@@ -12,6 +12,8 @@
 
 #include <kernel_arch_data.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifndef _ASMLANGUAGE
 
 #ifdef __cplusplus
@@ -20,7 +22,9 @@ extern "C" {
 
 static inline void arch_kernel_init(void)
 {
-	/* Nothing to be done */
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 static ALWAYS_INLINE void

arch/riscv/Kconfig

@@ -37,6 +37,38 @@ config RISCV_ALWAYS_SWITCH_THROUGH_ECALL
 	  and most people should say n here to minimize context switching
 	  overhead.
 
+choice RISCV_SMP_IPI_IMPL
+	prompt "RISC-V SMP IPI implementation"
+	depends on SMP
+	default RISCV_SMP_IPI_CLINT if DT_HAS_SIFIVE_CLINT0_ENABLED
+	default RISCV_SMP_IPI_PLIC if PLIC_SUPPORTS_SOFT_INTERRUPT && PLIC_IRQ_AFFINITY
+	default RISCV_SMP_IPI_CUSTOM
+
+config RISCV_SMP_IPI_CLINT
+	bool "CLINT-based IPI"
+	depends on DT_HAS_SIFIVE_CLINT0_ENABLED
+	help
+	  Use CLINT-based IPI implementation.
+
+config RISCV_SMP_IPI_PLIC
+	bool "PLIC-based IPI"
+	depends on PLIC_SUPPORTS_SOFT_INTERRUPT
+	depends on PLIC_IRQ_AFFINITY
+	help
+	  Use PLIC-based IPI implementation.
+
+config RISCV_SMP_IPI_CUSTOM
+	bool "Custom IPI implementation"
+	help
+	  Allow custom IPI implementation.
+
+	  When this is selected, the following functions must be provided:
+	   - z_riscv_ipi_send()
+	   - z_riscv_ipi_clear()
+	   - arch_smp_init()
+
+endchoice # RISCV_SMP_IPI_IMPL
+
 menu "RISCV Processor Options"
 
 config INCLUDE_RESET_VECTOR

arch/riscv/core/ipi_clint.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_ARCH_RISCV_CORE_IPI_CLINT_H_
+#define ZEPHYR_ARCH_RISCV_CORE_IPI_CLINT_H_
+
+#include <zephyr/kernel.h>
+
+#define MSIP_BASE 0x2000000UL
+#define MSIP(hartid) ((volatile uint32_t *)MSIP_BASE)[hartid]
+
+static ALWAYS_INLINE void z_riscv_ipi_send(unsigned int cpu)
+{
+	MSIP(_kernel.cpus[cpu].arch.hartid) = 1;
+}
+
+static ALWAYS_INLINE void z_riscv_ipi_clear(unsigned int cpu)
+{
+	MSIP(_kernel.cpus[cpu].arch.hartid) = 0;
+}
+
+static void sched_ipi_handler(const void *unused)
+{
+	ARG_UNUSED(unused);
+
+	z_riscv_sched_ipi_handler(_current_cpu->id);
+}
+
+int arch_smp_init(void)
+{
+	IRQ_CONNECT(RISCV_IRQ_MSOFT, 0, sched_ipi_handler, NULL, 0);
+	irq_enable(RISCV_IRQ_MSOFT);
+
+	return 0;
+}
+
+#endif /* ZEPHYR_ARCH_RISCV_CORE_IPI_CLINT_H_ */

arch/riscv/core/ipi_impl.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Meta Platforms
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_ARCH_RISCV_CORE_IPI_IMPL_H_
+#define ZEPHYR_ARCH_RISCV_CORE_IPI_IMPL_H_
+
+void z_riscv_sched_ipi_handler(unsigned int cpu_id);
+
+#ifdef CONFIG_RISCV_SMP_IPI_CLINT
+#include "ipi_clint.h"
+#elif defined(CONFIG_RISCV_SMP_IPI_PLIC)
+#include "ipi_plic.h"
+#else /* CONFIG_RISCV_SMP_IPI_CUSTOM */
+inline void z_riscv_ipi_send(unsigned int cpu);
+inline void z_riscv_ipi_clear(unsigned int cpu);
+int arch_smp_init(void);
+#endif
+
+#endif /* ZEPHYR_ARCH_RISCV_CORE_IPI_IMPL_H_ */

arch/riscv/core/ipi_plic.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2024 Meta Platforms
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_ARCH_RISCV_CORE_IPI_PLIC_H_
+#define ZEPHYR_ARCH_RISCV_CORE_IPI_PLIC_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/interrupt_controller/riscv_plic.h>
+#include <zephyr/irq_multilevel.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/util.h>
+
+#define DT_DRV_COMPAT zephyr_ipi_plic
+
+#define IPI_PLIC_IRQS(n, _) DT_INST_IRQN_BY_IDX(0, n)
+
+/* Should get this from the devicetree, placeholder now */
+static const uint32_t ipi_irqs[CONFIG_MP_MAX_NUM_CPUS] = {
+	LISTIFY(CONFIG_MP_MAX_NUM_CPUS, IPI_PLIC_IRQS, (,)),
+};
+
+static ALWAYS_INLINE void z_riscv_ipi_send(unsigned int cpu)
+{
+	riscv_plic_irq_set_pending(ipi_irqs[cpu]);
+}
+
+static ALWAYS_INLINE void z_riscv_ipi_clear(unsigned int cpu)
+{
+	ARG_UNUSED(cpu);
+	/* IRQ will be cleared by PLIC */
+}
+
+static void sched_ipi_handler(const void *arg)
+{
+	unsigned int cpu_id = POINTER_TO_UINT(arg);
+
+	z_riscv_sched_ipi_handler(cpu_id);
+}
+
+#define IPI_PLIC_IRQ_CONNECT(n, _)                                                                 \
+	IRQ_CONNECT(DT_INST_IRQN_BY_IDX(0, n), 1, sched_ipi_handler, UINT_TO_POINTER(n), 0);       \
+	irq_enable(n);                                                                             \
+	riscv_plic_irq_set_affinity(n, BIT(n))
+
+int arch_smp_init(void)
+{
+	LISTIFY(CONFIG_MP_MAX_NUM_CPUS, IPI_PLIC_IRQ_CONNECT, (;));
+
+	return 0;
+}
+
+#endif /* ZEPHYR_ARCH_RISCV_CORE_IPI_PLIC_H_ */